Sometimes, when changing frequency, a glitch can be seen on the output of a VCO being driving by the ADF4158 or ADF4159; that is, for a very short amount of time, the VCO outputs the wrong frequency before returning to the desired frequency.
This can be solved in by changing some register bits. There are four possible solutions:
- Set N SEL (R3, DB15) to 1.
N SEL – if the INT and FRAC values are reprogrammed, internally the INT value changes 4 PFD cycles before the FRAC value, temporarily outputting the wrong frequency. Enabling N SEL (setting bit to 1) ensures INT and FRAC change at the same time. See page 19 of Rev. E datasheet for more information. - Set S-D Reset (R3, DB14) to 1.
S-D Reset – after a write to R0, the S-D modulator is reset. This is to create a repeatable spur pattern. However, again, this can cause the part to temporarily output the wrong frequency. Enabling S-D Reset (setting bit to 1), removes this reset. See page 19 of datasheet. - Set LE SEL (R4, DB31) to 1.
LE SEL – there can be an internal timing glitch in the ADF4159 if the rising-edge of LE on a register write occurs at the same time as a rising-edge of the reference signal. Enabling LE SEL (setting bit to 1), synchronizes the rising-edge of LE with the falling-edge of the reference signal. See page 21 of the datasheet. - Set CLK DIV MODE (R4, DB[20:19]) to 00.
CLK DIV MODE – if the Ramp features are not being used, these bits should be set to 00.
