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Configuration

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The user is configuring a device to use two independent ADCs with the same sample rate, each ADC data path using two lanes of JESD204C. The settings for a single ADC are L = 2, M = 1, F = 3, and S = 4 with E = 3. For both ADCs, the user needs to set L = 4 and ensure data is correctly mapped to the lanes, which will be split between two QSFP28 cages.
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Category: Hardware
Product Number: AD9207

We are wanting to use this device as two independent ADCs using the same sample rate. I need to configure each ADC data path to use two lanes of JESD204C, i.e. use a total of four lanes from the device. I believe that I can map each ADC output to virtual ports and then map each virtual port to a lane. The settings for a JESD204C link will be  L = 2, M = 1, F = 3 and S = 4 with E = 3 for a single ADC. If I want to configure to use both ADCs do I have to set L = 4 and assume that the data from the two ADCs will be transported on the correct lanes. The situation is further complicated by the fact that all four lanes will not go to the same QSFP28 cage, they will be split between two cages.

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  • Hi,

    I am working my way through UG1587 and would like clarification on one point. The system will use both ADCs and use separate JESD204C configurations. The data to be transferred will be the raw data from the ADC's, i.e. both the Coarse DDCs and the Fine DDC's will be bypassed. I am making the assumption that if I leave Mux3 at its default settings then the data from ADC0 will appear at virtual output DFOUT0 and the data from ADC1 will appear at DFOUT2. Can you please confirm this assumption

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  • Hi,

    I am working my way through UG1587 and would like clarification on one point. The system will use both ADCs and use separate JESD204C configurations. The data to be transferred will be the raw data from the ADC's, i.e. both the Coarse DDCs and the Fine DDC's will be bypassed. I am making the assumption that if I leave Mux3 at its default settings then the data from ADC0 will appear at virtual output DFOUT0 and the data from ADC1 will appear at DFOUT2. Can you please confirm this assumption

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