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Configuration

Thread Summary

The user is configuring a device to use two independent ADCs with the same sample rate, each ADC data path using two lanes of JESD204C. The settings for a single ADC are L = 2, M = 1, F = 3, and S = 4 with E = 3. For both ADCs, the user needs to set L = 4 and ensure data is correctly mapped to the lanes, which will be split between two QSFP28 cages.
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Category: Hardware
Product Number: AD9207

We are wanting to use this device as two independent ADCs using the same sample rate. I need to configure each ADC data path to use two lanes of JESD204C, i.e. use a total of four lanes from the device. I believe that I can map each ADC output to virtual ports and then map each virtual port to a lane. The settings for a JESD204C link will be  L = 2, M = 1, F = 3 and S = 4 with E = 3 for a single ADC. If I want to configure to use both ADCs do I have to set L = 4 and assume that the data from the two ADCs will be transported on the correct lanes. The situation is further complicated by the fact that all four lanes will not go to the same QSFP28 cage, they will be split between two cages.

  • Hi @Camber

    Thanks for your question! Just a quick note to let you know we’ve received it and are currently working on it. We’ll get back to you soon with an update.

     

    Appreciate your patience.

  • I have been looking through UG1578 in order to understand the registers and how they are set. I am slightly confused but I think I know what the answer is. Figure 47, page 60, in the document shows COARSE DDC0 through to COARSE DDC3 and FINE DDC0 through to FINE DDC7.the label  However the register description for register at address 0x0281, page 309 of the user guide, describes mapping Coarse DDC1 through to Coarse DDC4 and Fine DDC1 through to Fine DDC8. I am assuming that if COARSE DDC0 in Fig 47 is replaced with COARSE DDC1 etc then the doument will be consistent.

  • Hi  , 

    Register description of address 0x0281 - COARSE_FINE_CB is incorrect. Please subtract 1 from all instances of DDCdescriptions

    For example, 

    In correct  Correct
    Bit[0] - 0 connects Coarse DDC1 to Fine DDC1 and
    1 connects Coarse DDC2 to Fine DDC1.
    Bit[0] - 0 connects Coarse DDC0 to Fine DDC0 and
    1 connects Coarse DDC1 to Fine DDC0.

    It's a good catch.

  • Hi @Camber,
    You can find the MxFE JESD204 Mode Selector Tool on the AD9207 product page under the Tools & Simulations section. The tool is available here:
    https://www.analog.com/en/license/licensing-agreement/jesd204-mode-selector-tool.html


    For guidance on using the tool, please refer to UG-1578—specifically the section titled “JESD204B/C Mode Selector Tool and Transmitter Mode Tables.” This will help you identify a suitable JESD mode for your setup.
    Let me know if you have any questions.

  • Hi,

    I am working my way through UG1587 and would like clarification on one point. The system will use both ADCs and use separate JESD204C configurations. The data to be transferred will be the raw data from the ADC's, i.e. both the Coarse DDCs and the Fine DDC's will be bypassed. I am making the assumption that if I leave Mux3 at its default settings then the data from ADC0 will appear at virtual output DFOUT0 and the data from ADC1 will appear at DFOUT2. Can you please confirm this assumption