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AD9986 Recommended for New Designs
The AD9986 is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate RF DAC core, and a 12-bit, 6 GSPS rate RF ADC core. The AD9986 supports...
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AD9986 valid interpolator settings

		
	
				

			

									
					    djs3f
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Apr 23, 2026 
				
			
			
		
    
		
		                    	    
    
        	    
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                The user inquired about the differences in interpolation values for AD9986 Mode 18 between JESD204B and JESD204C. The support engineer explained that the differences are due to changes in link parameters (F, S, K, and E) between the two standards, which affect the valid interpolation modes. The user also asked about Mode 16.00 decimation configurations, specifically why a total decimation of 12 allows coarse 6, fine 2 but not coarse 4, fine 3. The engineer indicated that this is an architectural limitation, not a validation issue.
                        	    
    
                
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    Category: Datasheet/Specs
    
    		        		            		    
    Product Number:  AD9986 
    
    		        		    		    
    
		    		    
		    			
    
			    
    For the AD9986 table 92 in UG-1578 indicates that mode 18 allows for 8 lanes for two converters running with a wide variety of coarse interpolation values (1,2,4,6,8x1) in JESD204B mode.  However table 93 indicates that mode 18 in JESD204C mode only runs with interpolation values of .  1x1, 2x1, 2x2, and 4x1.  Is this a documentation issue?  An actual hardware limitation?  A matter of some modes not being validated by ADI?  Why the difference between 204B and 204C?
    
			
    
			
									
		                             
                        

    
    
                                            
                 Datasheet/Specs
                
                                                    
                 A/D and D/A Converter Combinations
                
                                                    
                 AD9986
                
                                                    
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Apr 24, 2026 2:22 PM
            
            
						
			            		
      
		
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      Hi Daniel,
       
      I will look into this for you and advise.
       
      Thanks,
      Joe
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
				
				
				
		
		
      
			
		
      
	
      

      

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                on Apr 29, 2026 3:55 PM
            
            
						
			            		
        
		
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        Thanks Joe! 
        

        A similar question.  Mode 16.00 receive with a total decimation of 12 lists coarse 6, fine 2 as a valid combo, but not coarse 4, fine 3.  Same question as above - is this a matter of one config being validated and another not validated, or an actual limitation of the chip.  See the pasted in portion from page 139 of the user guide:
        

         
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
				
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
						
                            
            
            				
            
                on Apr 29, 2026 6:02 PM
            
            
						
			            		
        
		
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        Hi Daniel,
         
        The differences in interpolation modes that you are seeing between JESD204B Mode 18 and JESD204C Mode 18 are architectural, not a matter of validation.
         
        For JESD204B Mode 18, the link parameters are as follows:
         
        L = 8 
        M = 2 
        F = 2 
        S = 4 
        K = 32 
        N = 16 
        NP = 16
         
        Where:
         
        L = number of lanes 
        M = number of converters 
        F = octets per frame per lane 
        S = samples per converter per frame 
        N = sample resolution 
        NP = transmitted bits 
        K = frames per multiframe
         
        For JESD204C Mode 18, the link parameters change:
         
        L = 8 
        M = 2 
        F = 1 
        S = 2 
        K = 256 
        E = 1
        N = 16 
        NP = 16
         
        E in this case is the number of multiblocks in an extended multiblock.
         
        The difference in link parameters between 204B and 204C, which I've highlighted above, changes what valid interpolation modes exist. This also applies to Mode 16, and other Modes in JESD204B/JESD204C. 
         
        Please see this application note for more information on JESD204C: JESD204C Primer: What’s New and in It for You—Part 2 | Analog Devices
         
        Thanks,
        Joe
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
						
				
				
				
		
		
        
			
		
        
	
        

        

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                on Apr 30, 2026 9:19 AM
            
            
						
			            		
          
		
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          Thanks Joe,
          

          Follow-up on the mode 16 question.  Those are both JESD204C configs that I'm wondering about.  Why does 16.0 support 6x2 decimation, but not 4x3 decimation?  It results in the same sample rate leaving the FDDC towards the JESD mapper, so it doesn't make sense to me why we can't get to x12 decimation in two different ways.
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
				
				
				
		
		
          
			
		
          
	
          

          

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                on May 6, 2026 1:43 PM
            
            
						
			            		
            
		
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            Following up again - it looks like mode 32.00 supports both 4x3 and 6x2 decimation for total decimation of 12, but that mode transfers 24 bits per sample across the JESD link, requiring 50% faster clock speeds.  Is it really the case that the equivalent 16.00 mode only supports 6x2 decimation, and not 4x3?
            Highlighting the two modes below for reference:
             
            

             
            

            We're running up at 6 gsps.  It seems like the data path (CDDC, FDDC) can handle the data rates with 4x3 decimation based on the mode 32 options, and it's not clear why the JESD layer would how the decimation was split between fine and coarse as long as the total decimation equals 12.  For our application we'd much rather not move to mode 32 which stresses the JESD lanes more, and draws more power, so any feedback on the plausibility of the highlighted mode 16 supporting 4x3 decimation would be much appreciated.
            

            Thanks!
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
				
				
				
		
		
            
			
		
            
	
            

            

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