Category: Software
Product Number: AD9081
Hi ,
I require to bringup the JESD204C link between my zu15eg zynqmp FPGA and AD9081. My dtsi snippet section pertaining to AD9081 is shown below.
Tx Jesd Mode:
Rx Jesd Mode:
/include/ "system-conf.dtsi"
/ {
chosen {
bootargs = "earlycon clk_ignore_unused uio_pdrv_genirq.of_id=generic-uio";
stdout-path = "serial0:115200n8";
};
};
/ {
state_align {
compatible = "generic-uio";
status = "okay";
interrupt-parent = <&gic>;
interrupts = <0 92 1>;
};
};
/ {
rx_fixed_linerate: clock@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <10813440>;
clock-output-names = "rx_lane_clk";
};
tx_fixed_linerate: clock@3 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <10813440>;
//clock-frequency = <16220160>;
clock-output-names = "tx_lane_clk";
};
fixed_clk: fixed-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1179620000>;
clock-output-names = "support_clk";
};
adf4377_clkin: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <491520000>;
};
clocks {
dummy_ad9081_clk: clock@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
// clock-frequency = <1179648000>; // Default value
//clock-frequency = <491520000>;
clock-frequency = <327680000>;
//clock-frequency = <368640000>;
clock-output-names = "direct_clk_12000m";
};
};
};
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
&gem0 {
phy-mode = "sgmii";
is-internal-pcspma = "true";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&spi1 {
status = "okay";
num-cs = <1>;
hmc7044: hmc7044@0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <100000>;
interrupt-parent = <&gic>;
interrupts = <0 93 1>;
jesd204-device;
#jesd204-cells = <2>;
// jesd204-sysref-provider;
adi,hmc-two-level-tree-sync-en;
adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
adi,pll1-clkin-frequencies = <122880000 0 0 0>;
adi,pll1-loop-bandwidth-hz = <200>;
adi,vcxo-frequency = <122880000>;
adi,pll1-charge-pump-current-ua = <720>;
adi,pll2-output-frequency = <2949120000>;
adi,sysref-timer-divider = <256>;
adi,sync-pin-mode = <1>;
adi,clkin0-buffer-mode = <0x7>;
adi,oscin-buffer-mode = <0x7>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x37 0x00 0x00>;
clock-output-names =
"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c0: channel@0 {
reg = <0>;
adi,extended-name = "RF_PLL_C_CLK";
adi,divider = <9>; /* 327.68Mhz */
adi,driver-mode = <2>;
};
hmc7044_c1: channel@1 {
reg = <1>;
adi,extended-name = "AD9081_C_CLK";
adi,divider = <1152>; /* 1.28MHz*/
adi,driver-mode = <2>;
adi,jesd204-sysref-chan;
};
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "JESD_C_GTREFCLK1";
adi,divider = <18>; /* 163.84MHz */
adi,driver-mode = <2>;
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "C_FPGA_SYSREF1";
adi,divider = <1152>; /* 1.28Mhz */
adi,driver-mode = <2>;
adi,jesd204-sysref-chan;
};
hmc7044_c4: channel@4 {
reg = <4>;
adi,extended-name = "JESD_C_GTREFCLK2";
adi,divider = <18>; /* 163.84MHz */
adi,driver-mode = <2>;
};
hmc7044_c6: channel@6 {
reg = <6>;
adi,extended-name = "JESD_C_DEVCLK1";
adi,divider = <18>; /* 163.84MHz */
adi,driver-mode = <2>;
};
hmc7044_c8: channel@8 {
reg = <8>;
adi,extended-name = "JESD_C_DEVCLK2";
adi,divider = <24>; /* 122.88 Mhz */
adi,driver-mode = <2>;
};
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "DBG_C_CLK";
adi,divider = <24>; /* 122.88MHz */
adi,driver-mode = <2>;
};
};
};
&JESD_ad_ip_jesd204_tpl_adc_0 {
compatible = "adi,axi-ad9081-rx-1.0";
reg = <0x0 0x80000000 0x0 0x10000>;
/* dmas = <&rx_dma 0>;
dma-names = "rx";
*/
spibus-connected = <&trx0_ad9081>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&JESD_axi_jesd204_rx_0 0 FRAMER_LINK0_RX>;
};
&JESD_ad_ip_jesd204_tpl_dac_0 {
compatible = "adi,axi-ad9081-tx-1.0";
reg = <0x0 0x80010000 0x0 0x10000>;
/*
dmas = <&tx_dma 0>;
dma-names = "tx";
*/
clocks = <&trx0_ad9081 1>;
clock-names = "sampl_clk";
spibus-connected = <&trx0_ad9081>;
/*
//adi,axi-pl-fifo-enable;
adi,axi-data-offload-connected = <&axi_data_offload_tx>;
*/
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&JESD_axi_jesd204_tx_0 0 DEFRAMER_LINK0_TX>;
};
&JESD_axi_jesd204_rx_0 {
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x0 0x80020000 0x0 0x10000>;
interrupts = <0 90 4>;
clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&rx_fixed_linerate 0>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
#clock-cells = <0>;
clock-output-names = "jesd_rx_lane_clk";
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;
};
&JESD_axi_jesd204_tx_0 {
compatible = "adi,axi-jesd204-tx-1.0";
reg = <0x0 0x80030000 0x0 0x10000>;
interrupts = <0 89 4>;
clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&tx_fixed_linerate 0>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
#clock-cells = <0>;
clock-output-names = "jesd_tx_lane_clk";
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;
};
&qspi {
flash@0 {
compatible = "m25p80", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
};
};
&spi0 {
is-decoded-cs = <0>;
num-cs = <2>;
status = "okay";
trx0_ad9081:ad9081@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9081";
reg = <0>;
spi-max-frequency = <5000000>;
adi,jesd-sync-pin-0a-cmos-enable;
clocks = <&dummy_ad9081_clk>;
//dev_clk-clock-scales = <1 10>;
clock-names = "dev_clk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>; /* This is the TOP device */
jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
jesd204-ignore-errors;//TODO DEBUG ONLY REMOVE LATER
jesd204-inputs =
<&JESD_ad_ip_jesd204_tpl_adc_0 0 FRAMER_LINK0_RX>,
<&JESD_ad_ip_jesd204_tpl_dac_0 0 DEFRAMER_LINK0_TX>;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <10485760000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <4>;
ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&ad9081_tx_fddc_chan0>, <&ad9081_tx_fddc_chan1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
ad9081_dac1: dac@1 {
reg = <1>;
adi,crossbar-select = <&ad9081_tx_fddc_chan2>, <&ad9081_tx_fddc_chan3>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
ad9081_dac2: dac@2 {
reg = <2>;
adi,crossbar-select = <&ad9081_tx_fddc_chan4>, <&ad9081_tx_fddc_chan5>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
ad9081_dac3: dac@3 {
reg = <3>;
adi,crossbar-select = <&ad9081_tx_fddc_chan6>, <&ad9081_tx_fddc_chan7>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <4>;
ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan1: channel@1 {
reg = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan2: channel@2 {
reg = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan3: channel@3 {
reg = <3>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan4: channel@4 {
reg = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan5: channel@5 {
reg = <5>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan6: channel@6 {
reg = <6>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan7: channel@7 {
reg = <7>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <16>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <2>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <16>; /* JESD M */
adi,octets-per-frame = <4>; /* JESD F */
adi,frames-per-multiframe = <64>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <8>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
adi,tpl-phase-adjust = <0x3>;
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <2621440000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,digital-gain-6db-enable;
ad9081_adc0: adc@0 {
reg = <0>;
adi,decimation = <2>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
adi,crossbar-select = <&ad9081_rx_fddc_chan0>;
};
ad9081_adc1: adc@1 {
reg = <1>;
adi,decimation = <2>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
adi,crossbar-select = <&ad9081_rx_fddc_chan1>;
};
ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <2>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
adi,digital-gain-6db-enable;
adi,crossbar-select = <&ad9081_rx_fddc_chan4>;
};
ad9081_adc3: adc@3 {
reg = <3>;
adi,decimation = <2>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
adi,crossbar-select = <&ad9081_rx_fddc_chan5>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,digital-gain-6db-enable;
ad9081_rx_fddc_chan0: channel@0 {
reg = <0>;
adi,decimation = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan1: channel@1 {
reg = <1>;
adi,decimation = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan5: channel@5 {
reg = <5>;
adi,decimation = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>,
<&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
<&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <16>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <2>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <8>; /* JESD M */
adi,octets-per-frame = <2>; /* JESD F */
adi,frames-per-multiframe = <128>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <8>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
};
};
};
};
spidev@1 {
compatible = "lwn,bk4";
reg = <1>;
status = "okay";
spi-max-frequency = <10000000>;
};
};The build taken with the above dtsi gives me the below result.
163.84 Mhz was the clock provided as device clock to the jesd. why is the reported and measured device clock along with with link clock being overriden to 294.912 ?
Attaching the dmesg logs as well:
[ 23.715971] platform 80000000.ad_ip_jesd204_tpl_adc: deferred probe pending [ 23.722953] platform 80010000.ad_ip_jesd204_tpl_dac: deferred probe pending [ 23.729912] platform 80020000.axi_jesd204_rx: deferred probe pending [ 23.736263] platform 80030000.axi_jesd204_tx: deferred probe pending [ 347.799240] audit: type=1006 audit(1667916354.348:2): pid=958 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=1 res=1 [ 347.811551] audit: type=1300 audit(1667916354.348:2): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=7fce9b94f0 a2=1 a3=0 items=0 ppid=1 pid=958 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=1 comm="(systemd)" exe="/lib/systemd/systemd" key=(null) [ 347.836705] audit: type=1327 audit(1667916354.348:2): proctitle="(systemd)" [ 349.124823] audit: type=1006 audit(1667916355.672:3): pid=951 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=2 res=1 [ 349.137117] audit: type=1300 audit(1667916355.672:3): arch=c00000b7 syscall=64 success=yes exit=1 a0=7 a1=7fd0f313f0 a2=1 a3=1 items=0 ppid=1 pid=951 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=2 comm="sshd" exe="/usr/sbin/sshd" key=(null) [ 349.161384] audit: type=1327 audit(1667916355.672:3): proctitle=737368643A20726F6F74205B707269765D [ 358.889429] hmc7044 spi2.0: PLL1: Acquisition, CLKIN0 @ 122880000 Hz, PFD: 7680 kHz - PLL2: Locked @ 2949.120000 MHz [ 358.903749] axi-jesd204-rx 80020000.axi_jesd204_rx: AXI-JESD204-RX (1.07.a) at 0x80020000. Encoder 64b66b, width 8/8, lanes 8, jesd204-fsm. [ 358.917297] axi-jesd204-tx 80030000.axi_jesd204_tx: AXI-JESD204-TX (1.06.a) at 0x80030000. Encoder 64b66b, width 8/8, lanes 8, jesd204-fsm. [ 381.248678] ad9081 spi1.0: supply vdd not found, using dummy regulator [ 382.508558] ad9081 spi1.0: AD9081 Rev. 3 Grade 10 (API 1.6.0) probed [ 382.540271] cf_axi_adc 80000000.ad_ip_jesd204_tpl_adc: ADI AIM (10.03.) at 0x80000000 mapped to 0x000000003eb4f096 probed ADC AD9081 as MASTER [ 382.575081] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition initialized -> probed [ 382.585802] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition initialized -> probed [ 382.596508] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition probed -> initialized [ 382.607209] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition probed -> initialized [ 382.617914] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition initialized -> probed [ 382.628612] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition initialized -> probed [ 382.639308] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition probed -> idle [ 382.649400] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition probed -> idle [ 382.659498] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> device_init [ 382.670026] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> device_init [ 382.680559] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> link_init [ 382.691516] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> link_init [ 382.702482] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> link_supported [ 382.713703] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> link_supported [ 382.725340] hmc7044 spi2.0: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode [ 382.734456] axi-jesd204-tx 80030000.axi_jesd204_tx: axi_jesd204_tx_jesd204_link_pre_setup: Link0 set REFCLK to device/link rate 327680000 Hz failed (-22) [ 382.748196] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_pre_setup [ 382.759855] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_pre_setup [ 382.804113] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 [ 382.815857] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 [ 382.827601] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 [ 382.839425] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 [ 382.851451] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 [ 382.863281] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 [ 382.875117] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup [ 382.886513] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup [ 382.903231] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_setup -> opt_setup_stage1 [ 382.914714] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_setup -> opt_setup_stage1 [ 382.932954] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 [ 382.944954] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 [ 382.957143] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 [ 382.969148] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 [ 382.981155] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 [ 382.993154] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 [ 383.005152] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 [ 383.017154] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 [ 383.033356] ad9081 spi1.0: running jesd_rx_calibrate_204c, LR 21626880 kbps [ 386.501605] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable [ 386.513367] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable [ 386.525199] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clocks_enable -> link_enable [ 386.536509] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clocks_enable -> link_enable [ 386.797281] axi-jesd204-rx 80020000.axi_jesd204_rx: axi_jesd204_rx_jesd204_link_running: Link2 status failed (WAIT_BS) [ 386.807986] jesd204: /amba_pl@0/axi_jesd204_rx@80020000,jesd204:4,parent=80020000.axi_jesd204_rx: JESD204[0:2] In link_running got error from cb: -1 (ignoring!) [ 386.833628] ad9081 spi1.0: JESD RX (JTX) Link2 PLL locked, PHASE established, MODE valid [ 386.925615] ad9081 spi1.0: JESD TX (JRX) Link0 204C status: Undef (1) [ 386.932053] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] In link_running got error from cb: -1 (ignoring!) [ 386.944234] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_enable -> link_running [ 386.955457] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_enable -> link_running [ 386.966686] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_running -> opt_post_running_stage [ 386.978866] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_running -> opt_post_running_stage [ 386.991105] cf_axi_dds 80010000.ad_ip_jesd204_tpl_dac: Analog Devices CF_AXI_DDS_DDS MASTER (9.02.b) at 0x80010000 mapped to 0x000000004b6e2e3f, probed DDS AD9081
Edit Notes
Attaching dmesg log[edited by: AflahAfu at 5:11 AM (GMT -5) on 21 Feb 2026]