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Interfacing AD9082 JESD204C with Versal GTM

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The user is troubleshooting a JESD204C link between AD9082 and Xilinx Versal GTM transceivers. After fixing CRC-12 issues by adjusting the 64B66B header and data placement, the PN7 sequence passes on the FPGA-to-DAC link, but the MxFE occasionally reports LANE_FIFO_EMPTY. The Analog Devices engineer suggests this flag may indicate minor clock wander and recommends running a long-term PN31 test to build confidence in the link stability.
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Category: Hardware
Product Number: AD9082

I am trying bring up a JESD204C link between a MxFE AD9082 and Xilinx Versal GTM transceivers. The GTM transceivers don't have the built in 64b66b ASYNC gearbox. Are there any example designs using ADI's JESD HDL IP interfacing with Xilinx Versal GTMs using JESD204C?

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