JESD204C Lane not getting up

Hello,

With regard to description "Using HMC to generate 125 MHz as CLK and Feeding 4.4GHz (5dBm) to EXT_CLK input of AD9082 and bypassing the PLL, capacitors C4D & C6D are mounted and C3D and C5D are un-mounted"............................it would appear that the "SERDES REFCLK" is either not being provided and/or is not locked to the 4.4 GHz external clock signal.   For a successful JESD204 link to occur.............both the clock provided to the AD9082  (i.e. EXT_CLK in your case) as well as the reference clock provided to FPGA (which is used by its SERDES PLL) must be phase locked to ensure that the lane rates are at exactly the same frequency and are phase aligned (i.e. no drift in phase).   Note that when one uses the HMC7044 to provide both the clock to the AD9082 as well as the ref clock (via FMC connector pins).................these two signals being derived off the same HMC PLL2/VCO are considered locked.

With regard to your settings...................the SPI writes that occur should be based on the AD9082  API which generates all the necessary SPI writes to configure the device (as well as exact order in which they must occur).  It is unclear from your description on whether the AD9082 SPI configuration file is based on our API.  

Note that our ACE based GUI provides a means of configuring the AD9082 from a high level when interfacing to our ADS9-V2 FPGA capture board.  One can inspect the "SPI writes" used to configure the device via downloading the log file.  Assuming that you have a ADS9-V2 board..............perhaps it would be best to use this 1st to verify that your desired configuration does work before moving to implement on another FPGA platform.  Note that the Tx (and Rx) ref clock corresponds to the clock frequency that is required by the FPGA to that its clocks are phase aligned with the AD9082.  In the case of applying an external ref clock to the AD9082 FMCA EVB...............one must also apply an external reference clock to the FPGA via another RF generator that is phase locked (via 10 MHz REF OUT/IN connection on back of instrument with master/slave relationship).

Regards