Mixed-Signal Front Ends (MxFE)

Q&A

by apal4 Mixed-Signal Front Ends (MxFE)

Started 9 hours ago

14 0 0

Not Answered
FFH control in GPIO Direct Mode in Kuiper Linux 0
Not Answered

Hello, I am trying to test the AD9084_EBZ GPIO hop mode, using a VPK180 running Kuiper Linux, but facing difficulties. Here is what I have done so far: I am using device-profile-fw-name = "204C_M4_L4_NP16_20p0_4x4.bin", which has the quick profile...

software A/D and D/A Converter Combinations AD9084 Kuiper Linux AD9088 gpio linux Show More

14 0 0
by ETHAN97 Mixed-Signal Front Ends (MxFE)

Started 1 day ago

11 0 2

Not Answered
Poor Signal Quality on Custom AD9988 Board – Different AC-Coupling and Extra Limiter Compared to Eval Board 0
Not Answered

Hardware Setup Comparison: Our Custom Board Evaluation Board Signal Path SMP → 0.1µF Capacitor → Balun (RLM-33H+) → Limiter → P/N connected directly to AD9988 SMP → 0.1µF Capacitor → Balun → 0.1µF Capacitors in series...

adc hardware AD9988 A/D and D/A Converter Combinations jesd204c RLM-33H+ limiter balun Signal Integrity Show More

11 0 2
by shiba183 Mixed-Signal Front Ends (MxFE)

Latest 2 days ago by Satoru
32 1 0
Not Answered
2channel ADC channles simulatenouey using AD9080-FMCA-EBZ &ADS10 0
Not Answered

Hello My customer intends to purchasse AD9084-FMCA-EBZ and ADS10-V1EBZ. Here is customers question. == Q1 I want to estimate about how many ADC channles can be used simulatenously using A D9084-FMCA-EBZ and ADS10-V1EBZ prior to purchase. ...

Datasheet/Specs A/D and D/A Converter Combinations AD9084 High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) Show More

32 1 0
by Steve9 Mixed-Signal Front Ends (MxFE)

Latest 7 days ago by Steve9

394 7 1

Suggested Answer
AD9081 SYSREF Input Voltage Datasheet/User Guide Discrepancy +1
Suggested Answer

Hi, The AD9081 Datasheet (link) indicates SYSREF_P/N input differential voltage is 0.7V min and 1.9V max differential pk-pk. However the AD9081/AD9082 SW Development UG, UG-1578 (link) indicates it's 0.2V min and 2.0V max differential pk-pk ...

Datasheet/Specs Clock Generation and Distribution Clock Distribution Devices AD9081 High Speed A/D Converters >10 MSPS sysref Mixed-Signal Front Ends (MxFE) hmc7043 Show More

394 7 1
by OR1 Mixed-Signal Front Ends (MxFE)

Latest 7 days ago by yhkim
199 7 0
Not Answered
No Link on AD9082 + ZynqMP Custom Board 0
Not Answered

Hello, I'm currently facing a problem deploying the reference design for ZCU102+AD9082 on a custom board with specific parameters. First I tried to port a design with the default parameters, as is: make JESD_MODE=8B10B \ RX_LANE_RATE=15 \ TX_LANE_RATE...

hardware Clock ICs A/D and D/A Converter Combinations clock and timing Inertial Measurement Units (IMU) petalinux Sensors and MEMS AD9082-FMCA-EBZ Mixed-Signal Front Ends (MxFE) AD9082 Show More

199 7 0
by Camber Mixed-Signal Front Ends (MxFE)

Latest 9 days ago by Camber

229 5 0

Answered
Configuration 0
Answered

We are wanting to use this device as two independent ADCs using the same sample rate. I need to configure each ADC data path to use two lanes of JESD204C, i.e. use a total of four lanes from the device. I believe that I can map each ADC output to virtual...

Analog to Digital Converters (ADCs) hardware AD9207 High Speed A/D Converters >10 MSPS

229 5 0
by TTB Mixed-Signal Front Ends (MxFE)

Started 13 days ago

42 0 0

Not Answered
Some question with AD9084 0
Not Answered

When using AD9084 chip with Xilinx FPGA, the following problems occurred. Firstly, under the condition that I can ensure the proper functioning of the SPI protocol (being able to correctly read and write various registers such as 0x0000h, 0x0134h, etc...

software A/D and D/A Converter Combinations AD9084

42 0 0
by bx3 Mixed-Signal Front Ends (MxFE)

Started 14 days ago

39 0 0

Not Answered
Apollo_Installer 0
Not Answered

Dear， Is the Apollo_Installer in the ACE software? How can I get it？

software A/D and D/A Converter Combinations AD9084

39 0 0
by mberger Mixed-Signal Front Ends (MxFE)

Latest 16 days ago by yhkim
128 1 0
Answered
AD9084 simple bring-up reference for JTAG-only access (no Linux/MicroZed) — VPK180 carrier 0
Answered

Hi all, I'm looking for a simple bring-up workflow for the AD9084 in a setup where: - The PS on the FPGA cannot (yet) run Linux - There's no MicroZed mezzanine - All access is JTAG-only via xsct, driving a PL-side axi_quad_spi core that connects to...

Phase-Locked Loop (PLL) Synthesizers Datasheet/Specs Apollo MxFE Clock ICs A/D and D/A Converter Combinations clock and timing AD9084 bring-up jesd204c rf and microwave Show More

128 1 0
by lbreuer Mixed-Signal Front Ends (MxFE)

Latest 16 days ago by yhkim
168 2 0
Not Answered
Problems getting the jrx links to work for certain lane rates 0
Not Answered

Hello everyone, I have trouble getting the jrx links on the AD9084 to work correctly. With all profiles generated with the ACE Software I have no problem transmitting data to my FPGA (VCU128), regardless of the lane rate. Receiving data on the Apollo...

hardware A/D and D/A Converter Combinations AD9084

168 2 0
by yuanciou Mixed-Signal Front Ends (MxFE)

Latest 17 days ago by William.WF.Chen
112 1 0
Answered
ADC AD9207's PLL doesn't locked(address 0x0701) 0
Answered

Hi : I am currently developing a custom PCB using the AD9207 dual-core ADC interfaced with an FPGA via JESD204C (SPI for register configuration). Previously, we successfully verified our FPGA firmware logic using the AD9081 EVM paired with a ZC706...

Analog to Digital Converters (ADCs) software AD9207 A/D and D/A Converter Combinations Vivado 2023.2 Show More

112 1 0
by yuanciou Mixed-Signal Front Ends (MxFE)

Latest 17 days ago by William.WF.Chen
99 1 0
Answered
ADC AD9207 PLL doesn't locked 0
Answered

Hi : I am currently designing a hardware system using the AD9207 dual-core ADC interfaced with an FPGA via JESD204C . The SPI interface is used to configure the internal registers. Our current system parameters and configurations are listed below...

Analog to Digital Converters (ADCs) software AD9207 Vivado 2023.2

99 1 0
by Guruthathath Mixed-Signal Front Ends (MxFE)

Latest 19 days ago by VenkateshKonduru
100 1 0
Answered
HDL CODE - VHDL REFERENCE (AD9084, VCK190) 0
Answered

Hi ADI team, I am currently facing an issue while cloning the HDL reference code to my PC and am unable to complete the process. Could you please provide the AD9084 reference design source code in VHDL? I Attached the Photos while cloning time what...

Datasheet/Specs A/D and D/A Converter Combinations AD9084 vck190

100 1 0
by Guruthathath Mixed-Signal Front Ends (MxFE)

Latest 1 month ago by Guruthathath

267 3 0

Answered
HDL CODE - VHDL REFERENCE (AD9084, VCK190) 0
Answered

Hi ADI Team, I am currently facing an issue while cloning the HDL reference code to my PC and am unable to complete the process. Could you please provide the AD9084 reference design source code in VHDL? I am using Vivado 2023.2 and working with the...

Datasheet/Specs A/D and D/A Converter Combinations AD9084 vck190

267 3 0
by djs3f Mixed-Signal Front Ends (MxFE)

Latest 1 month ago by djs3f

371 5 0

Answered
AD9986 valid interpolator settings 0
Answered

For the AD9986 table 92 in UG-1578 indicates that mode 18 allows for 8 lanes for two converters running with a wide variety of coarse interpolation values (1,2,4,6,8x1) in JESD204B mode. However table 93 indicates that mode 18 in JESD204C mode only runs...

Datasheet/Specs A/D and D/A Converter Combinations AD9986 Mixed-Signal Front Ends (MxFE)

371 5 0

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Q&A

Not Answered
FFH control in GPIO Direct Mode in Kuiper Linux 0
Not Answered

Not Answered
Poor Signal Quality on Custom AD9988 Board – Different AC-Coupling and Extra Limiter Compared to Eval Board 0
Not Answered

Not Answered
2channel ADC channles simulatenouey using AD9080-FMCA-EBZ &ADS10 0
Not Answered

Suggested Answer
AD9081 SYSREF Input Voltage Datasheet/User Guide Discrepancy +1
Suggested Answer

Not Answered
No Link on AD9082 + ZynqMP Custom Board 0
Not Answered

Answered
Configuration 0
Answered

Not Answered
Some question with AD9084 0
Not Answered

Not Answered
Apollo_Installer 0
Not Answered

Answered
AD9084 simple bring-up reference for JTAG-only access (no Linux/MicroZed) — VPK180 carrier 0
Answered

Not Answered
Problems getting the jrx links to work for certain lane rates 0
Not Answered

Answered
ADC AD9207's PLL doesn't locked(address 0x0701) 0
Answered

Answered
ADC AD9207 PLL doesn't locked 0
Answered

Answered
HDL CODE - VHDL REFERENCE (AD9084, VCK190) 0
Answered

Answered
HDL CODE - VHDL REFERENCE (AD9084, VCK190) 0
Answered

Answered
AD9986 valid interpolator settings 0
Answered

Q&A

Not Answered FFH control in GPIO Direct Mode in Kuiper Linux 0 Not Answered

Not Answered Poor Signal Quality on Custom AD9988 Board – Different AC-Coupling and Extra Limiter Compared to Eval Board 0 Not Answered

Not Answered 2channel ADC channles simulatenouey using AD9080-FMCA-EBZ &ADS10 0 Not Answered

Suggested Answer AD9081 SYSREF Input Voltage Datasheet/User Guide Discrepancy +1 Suggested Answer

Not Answered No Link on AD9082 + ZynqMP Custom Board 0 Not Answered

Answered Configuration 0 Answered

Not Answered Some question with AD9084 0 Not Answered

Not Answered Apollo_Installer 0 Not Answered

Answered AD9084 simple bring-up reference for JTAG-only access (no Linux/MicroZed) — VPK180 carrier 0 Answered

Not Answered Problems getting the jrx links to work for certain lane rates 0 Not Answered

Answered ADC AD9207's PLL doesn't locked(address 0x0701) 0 Answered

Answered ADC AD9207 PLL doesn't locked 0 Answered

Answered HDL CODE - VHDL REFERENCE (AD9084, VCK190) 0 Answered

Answered HDL CODE - VHDL REFERENCE (AD9084, VCK190) 0 Answered

Answered AD9986 valid interpolator settings 0 Answered

Not Answered
FFH control in GPIO Direct Mode in Kuiper Linux 0
Not Answered

Not Answered
Poor Signal Quality on Custom AD9988 Board – Different AC-Coupling and Extra Limiter Compared to Eval Board 0
Not Answered

Not Answered
2channel ADC channles simulatenouey using AD9080-FMCA-EBZ &ADS10 0
Not Answered

Suggested Answer
AD9081 SYSREF Input Voltage Datasheet/User Guide Discrepancy +1
Suggested Answer

Not Answered
No Link on AD9082 + ZynqMP Custom Board 0
Not Answered

Answered
Configuration 0
Answered

Not Answered
Some question with AD9084 0
Not Answered

Not Answered
Apollo_Installer 0
Not Answered

Answered
AD9084 simple bring-up reference for JTAG-only access (no Linux/MicroZed) — VPK180 carrier 0
Answered

Not Answered
Problems getting the jrx links to work for certain lane rates 0
Not Answered

Answered
ADC AD9207's PLL doesn't locked(address 0x0701) 0
Answered

Answered
ADC AD9207 PLL doesn't locked 0
Answered

Answered
HDL CODE - VHDL REFERENCE (AD9084, VCK190) 0
Answered

Answered
HDL CODE - VHDL REFERENCE (AD9084, VCK190) 0
Answered

Answered
AD9986 valid interpolator settings 0
Answered