Mixed-Signal Front Ends (MxFE)

Q&A

by Frita
Mixed-Signal Front Ends (MxFE)

Started 13 hours ago
16 0 0
Not Answered
Accuracy issues and parasitic capacitance trends with EVAL-AD5940BIOZ in 4-wire BIA mode 0
Not Answered

Hello, I am working with the EVAL-AD5940BIOZ evaluation kit for impedance spectroscopy, specifically using the 4-wire Body Impedance (BIA) mode in SensorPal. My current test setup uses a 100mV peak amplitude at 10kHz . I have already manually tuned...

hardware A/D and D/A Converter Combinations ad5940

16 0 0
by TomKunkel
Mixed-Signal Front Ends (MxFE)

Latest 1 day ago by yhkim
156 6 0
Not Answered
AD9084_EBZ interfacing to VCU118 - JESD204 lanes are not coming up 0
Not Answered

I am having an issue getting the AD9084 dev board working with the VCU118 dev board. Here are is my process for integrating these two boards. I am basically following the steps in this document. analogdevicesinc.github.io/.../microblaze.html Here...

Clock Generation Devices Clock Generation and Distribution Build Process hardware vcu118 Digital Step Attenuators Driver error A/D and D/A Converter Combinations AD9084 attenuators Show More

156 6 0
by UBOTI
Mixed-Signal Front Ends (MxFE)

Latest 1 day ago by UBOTI
36 1 0
Not Answered
Regarding abnormal regulator output voltage of AD9081 0
Not Answered

The AD9081 on our board is malfunctioning due to the following conditions. We suspect an internal power supply malfunction, but could you please advise the cause of this issue and any additional points to check? - After powering on the device, it heats...

Datasheet/Specs AD9081 High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE)

36 1 0
by Dhi
Mixed-Signal Front Ends (MxFE)

Latest 3 days ago by Dhi
384 11 0
Not Answered
Changing Sampling Rate from 250 MSPS to 375 MSPS using JESD204B with PetaLinux 0
Not Answered

I am working with an AD9081-based design on a Zynq UltraScale+ platform , using JESD204B and PetaLinux , and I am attempting to increase the sampling rate from 250 MSPS to 375 MSPS . To support 375 MSPS operation, I increased the JESD lane rate from...

Clock Generation Devices Clock Generation and Distribution hardware External Power Switch Buck Controllers High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) AD9081 with ZCU102 Step-Down (Buck) Regulators Show More

384 11 0
by yuanciou
Mixed-Signal Front Ends (MxFE)

Latest 9 days ago by William.WF.Chen
50 1 0
Suggested Answer
AD9081 JTX_PLL_LOCKED failed 0
Suggested Answer

I'm currently using the AD9081 EVM in conjunction with the ZC706 carrier board for ADC data acquisition via the JESD204B/C interface. However, I have encountered an issue where the FPGA is not receiving K28.5 symbols from the ADC. Upon inspecting the...

software AD9081 AD9081-FMCA-EBZ High Speed A/D Converters >10 MSPS Vivado 2023.2 Mixed-Signal Front Ends (MxFE) Show More

50 1 0
by OR1
Mixed-Signal Front Ends (MxFE)

Latest 14 days ago by OR1
233 4 0
Not Answered
AD9082 - tx data is not continuous 0
Not Answered

Hello, I'm currently facing a problem using the reference design for VPK180+AD9082 for the board VPK120. The ADC path works fine, but the data transmitted from the DAC path is not continuous, but in bursts - toggling at about 50Hz. I Identified a possible...

Clock Generation Devices Clock Generation and Distribution hardware High Speed A/D Converters >10 MSPS jesd204c Mixed-Signal Front Ends (MxFE) AD9082 Show More

233 4 0
by Daniel.B
Mixed-Signal Front Ends (MxFE)

Latest 15 days ago by THA
512 21 0
Answered
ACE software errors out and times out on ADS10 0
Answered

I am using the ACE software to test various configurations of the Apollo demo card. Half the time, it will error out initializing the card. Other times it will say it initialized correctly, but then fails in Rx capture or Tx download. The error usually...

hardware ADS10 A/D and D/A Converter Combinations AD9084 ace ad9084_evaluation_sw_0.21.1 Show More

512 21 0
by UVLSIDRIVER
Mixed-Signal Front Ends (MxFE)

Started 15 days ago
40 0 0
Not Answered
AD9081 Multi-Chip Synchronization Issue: Two ADCs Individually Aligned but Not Phase-Aligned Across Chips 0
Not Answered

Hello everyone, I am working with a dual AD9081 ADC system interfaced to a Xilinx XCZU15EG-1156FFVB-1-I FPGA. Both AD9081 devices share the same device clock and the same SYSREF source . System Overview 2 × AD9081 ADCs Each ADC: 4 channels...

software AD9081 High Speed A/D Converters >10 MSPS multichipsync Mixed-Signal Front Ends (MxFE) 2018.3 phase Show More

40 0 0
by GAllott
Mixed-Signal Front Ends (MxFE)

Latest 17 days ago by yhkim
99 1 0
Not Answered
deleted 0
Not Answered

deleted

Clock Generation Devices Clock Generation and Distribution hardware AD9081 High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) 9081 Show More

99 1 0
by yuanciou
Mixed-Signal Front Ends (MxFE)

Started 17 days ago
49 0 0
Not Answered
AD9081's JTX PLL Lock Failure and Sync Issues on ZC706 Platform 0
Not Answered

I'm currently using the AD9081 EVM in conjunction with the ZC706 carrier board for ADC data acquisition via the JESD204B/C interface. However, I have encountered an issue where the FPGA is not receiving K28.5 symbols from the ADC. Upon inspecting the...

software AD9081 High Speed A/D Converters >10 MSPS Vivado 2023.2 Mixed-Signal Front Ends (MxFE) Show More

49 0 0
by Steve9
Mixed-Signal Front Ends (MxFE)

Started 17 days ago
41 0 0
Not Answered
AD9081 SYSREF Input Voltage Datasheet/User Guide Discrepancy 0
Not Answered

Hi, The AD9081 Datasheet (link) indicates SYSREF_P/N input differential voltage is 0.7V min and 1.9V max differential pk-pk. However the AD9081/AD9082 SW Development UG, UG-1578 (link) indicates it's 0.2V min and 2.0V max differential pk-pk ...

Datasheet/Specs Clock Generation and Distribution Clock Distribution Devices AD9081 High Speed A/D Converters >10 MSPS sysref Mixed-Signal Front Ends (MxFE) hmc7043 Show More

41 0 0
by yuanciou
Mixed-Signal Front Ends (MxFE)

Started 23 days ago
68 0 0
Not Answered
AD9081 JTX PLL Lock Failure and Sync Issues on ZC706 Platform 0
Not Answered

We are currently using the AD9081 EVM in conjunction with the ZC706 carrier board for ADC data acquisition via the JESD204B/C interface. However, we have encountered an issue where the FPGA is not receiving K28.5 symbols from the ADC. Upon inspecting...

hardware AD9081 High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE)

68 0 0
by Shil
Mixed-Signal Front Ends (MxFE)

Latest 24 days ago by yhkim
94 1 0
Not Answered
ad9081 example 10 in ug1578 for 375 MSPS 0
Not Answered

i am trying the given example .i have generated the bitstream by giving the following command "make JESD_MODE=8B10B TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=2 TX_LANE_RATE=15 RX_JESD_M=4 RX_JESD_L=1 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS...

hardware ad9081 + zcu102 board AD9081 High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) Show More

94 1 0
by Shil
Mixed-Signal Front Ends (MxFE)

Latest 24 days ago by Shil
195 5 0
Not Answered
ad9081 + data rate 375 MSPS 0
Not Answered

Hi all Right now i am working on following configuration for ad9081 board + zcu102 DAC sample rate = 12 GSPS Channel interpolation = 3 × Main interpolation = 8× Total interpolation = 24 × Digital resolution = 16-bit ...

jesd hardware lane rate AD9081 High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) Show More

195 5 0
by infinite
Mixed-Signal Front Ends (MxFE)

Latest 29 days ago by THA
942 22 0
Not Answered
Instantaneous bandwidth 0
Not Answered

Hello ADI team, Please tell me what is the maximum instantaneous bandwidth for AD9988. Can I generate LFM signal on all 4 DAC's with center frequency 4.8GHz and +/- 500 MHz bandwidth. Also can I receive on all 4 ADC's same LFM signal at centre frequency...

Datasheet/Specs AD9988 Wideband Transceiver IC RF Integrated Transceivers

942 22 0

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Q&A

Not Answered
Accuracy issues and parasitic capacitance trends with EVAL-AD5940BIOZ in 4-wire BIA mode 0
Not Answered

Not Answered
AD9084_EBZ interfacing to VCU118 - JESD204 lanes are not coming up 0
Not Answered

Not Answered
Regarding abnormal regulator output voltage of AD9081 0
Not Answered

Not Answered
Changing Sampling Rate from 250 MSPS to 375 MSPS using JESD204B with PetaLinux 0
Not Answered

Suggested Answer
AD9081 JTX_PLL_LOCKED failed 0
Suggested Answer

Not Answered
AD9082 - tx data is not continuous 0
Not Answered

Answered
ACE software errors out and times out on ADS10 0
Answered

Not Answered
AD9081 Multi-Chip Synchronization Issue: Two ADCs Individually Aligned but Not Phase-Aligned Across Chips 0
Not Answered

Not Answered
deleted 0
Not Answered

Not Answered
AD9081's JTX PLL Lock Failure and Sync Issues on ZC706 Platform 0
Not Answered

Not Answered
AD9081 SYSREF Input Voltage Datasheet/User Guide Discrepancy 0
Not Answered

Not Answered
AD9081 JTX PLL Lock Failure and Sync Issues on ZC706 Platform 0
Not Answered

Not Answered
ad9081 example 10 in ug1578 for 375 MSPS 0
Not Answered

Not Answered
ad9081 + data rate 375 MSPS 0
Not Answered

Not Answered
Instantaneous bandwidth 0
Not Answered

Q&A

Not Answered Accuracy issues and parasitic capacitance trends with EVAL-AD5940BIOZ in 4-wire BIA mode 0 Not Answered

Not Answered AD9084_EBZ interfacing to VCU118 - JESD204 lanes are not coming up 0 Not Answered

Not Answered Regarding abnormal regulator output voltage of AD9081 0 Not Answered

Not Answered Changing Sampling Rate from 250 MSPS to 375 MSPS using JESD204B with PetaLinux 0 Not Answered

Suggested Answer AD9081 JTX_PLL_LOCKED failed 0 Suggested Answer

Not Answered AD9082 - tx data is not continuous 0 Not Answered

Answered ACE software errors out and times out on ADS10 0 Answered

Not Answered AD9081 Multi-Chip Synchronization Issue: Two ADCs Individually Aligned but Not Phase-Aligned Across Chips 0 Not Answered

Not Answered deleted 0 Not Answered

Not Answered AD9081's JTX PLL Lock Failure and Sync Issues on ZC706 Platform 0 Not Answered

Not Answered AD9081 SYSREF Input Voltage Datasheet/User Guide Discrepancy 0 Not Answered

Not Answered AD9081 JTX PLL Lock Failure and Sync Issues on ZC706 Platform 0 Not Answered

Not Answered ad9081 example 10 in ug1578 for 375 MSPS 0 Not Answered

Not Answered ad9081 + data rate 375 MSPS 0 Not Answered

Not Answered Instantaneous bandwidth 0 Not Answered

Not Answered
Accuracy issues and parasitic capacitance trends with EVAL-AD5940BIOZ in 4-wire BIA mode 0
Not Answered

Not Answered
AD9084_EBZ interfacing to VCU118 - JESD204 lanes are not coming up 0
Not Answered

Not Answered
Regarding abnormal regulator output voltage of AD9081 0
Not Answered

Not Answered
Changing Sampling Rate from 250 MSPS to 375 MSPS using JESD204B with PetaLinux 0
Not Answered

Suggested Answer
AD9081 JTX_PLL_LOCKED failed 0
Suggested Answer

Not Answered
AD9082 - tx data is not continuous 0
Not Answered

Answered
ACE software errors out and times out on ADS10 0
Answered

Not Answered
AD9081 Multi-Chip Synchronization Issue: Two ADCs Individually Aligned but Not Phase-Aligned Across Chips 0
Not Answered

Not Answered
deleted 0
Not Answered

Not Answered
AD9081's JTX PLL Lock Failure and Sync Issues on ZC706 Platform 0
Not Answered

Not Answered
AD9081 SYSREF Input Voltage Datasheet/User Guide Discrepancy 0
Not Answered

Not Answered
AD9081 JTX PLL Lock Failure and Sync Issues on ZC706 Platform 0
Not Answered

Not Answered
ad9081 example 10 in ug1578 for 375 MSPS 0
Not Answered

Not Answered
ad9081 + data rate 375 MSPS 0
Not Answered

Not Answered
Instantaneous bandwidth 0
Not Answered