I am involved in a new design based on HMC699, I need to generate a 5920MHz signal with a reference input of 20MHz.
I have simulated the system using ADISim PLL and the chip programming assitant Gives me 37 (with other names) for the programming register, but from the datasheet I get A=36 S=0.
With A=37 the system would not work because it would give S=-8
Could someone tell me what is the correct value? Am I doing anything wrong?
Thanks in advance
The ADIsimPLL chip programming assistant values are not correct. Use the datasheet equations, A=36 and S=0.
Thank you very much for your reply.
We have built our prototype following the indications form the datasheet and the example circuit but it does not work, there is no Loop Lock and the HMC699 gets very very hot, could you help us with that?
Sorry to hear your having difficulty getting the HMC699 to lock.
I reviewed your schematic and the loop filter design, VCO input drive level and chip logic appear to be fine. I noticed that you are using a 20 MHz reference that utilizes an LVCMOS sine wave output. At lower reference frequencies,the reduced slew rate of a sine wave form requires higher drive levels. If you haven't already verified that the REF in drive level is at the proper level (probably +5 to +9 dBm for 20 MHz) I would encourage you to do so. As the slew rate increases, reduced drive levels are possible so if lower power consumption is a goal, an oscillator with a square wave output may help. The HMC4069 datasheet (similar PLL) illustrates how the residual phase noise is impacted by the reference input drive level and waveform. Also note that the REF / NREF input is 50 ohms differential or 25 ohms, single ended. The shunt 50 ohm resistor at the input will reduce the input impedance and increase the drive level but you may be over driving the HMC699 which may be why it is running hot. In our application example, at the end of the HMC699 datasheet we use a 100 MHz VCXO (not specified but it's a CMOS output) and directly drive the REF input. This case would typically require a 3-6 dB attenuator as about +13dBm results for a 50 ohm impedance. Unfortunately we don't provide much clarity regarding this in our apps circuit.
Another area that may be worth investigating is the actual Vtune voltage being delivered by the loop filter vs what is required for the actual VCO you are using. At 5920 MHz the datasheet for the VCO you're using shows that it falls near the upper end of it's range (~8.5 to 9V). However, the AD797 is only biased with +12V which may not be quite enough. The AD797 when biased with 15V will output a nominal +12 V to +13 V. Using a 12V bias this range will likely be in the +9 V to + 10V range. If the VCO needs 9.10 V it's not going to lock.
Regarding the high temp of the HMC699, be sure to verify the current that the HMC699 is drawing falls within the spec, ~345mA. Also verify that the layout is using the proper footprint footprint for the LP5 package which includes (16) 10 mil , thru hole (not blind) vias for maximum thermal transfer.
I have news about this design, sorry for being offline too much time.
Regarding the VCO we used you are right, we are working very close to the AD797 limits but we could not afford +15V power supply.
The VCOs are working outside the datasheet limits but we were told it should work. We have been able to lock our prototypes correctly but in some of them we had to sligthtly redesign the loop filter. The frequency error is very low and the phase noise is good.
Regarding the OCXO I will take a look to the drive levels as you recommend and see if we can adapt the reference correctly and also lower the temperature.
Regarding power consumption we are inside the datasheet limits. The PCB has all the vias you said but we will improve the heat dissipation.
Thank you very much for your help.