ADF4106 Digital Lock Detect

1)We need to know from Analog Devices if loading the ADF4106 Digital Lock Detect with a 1uF capacitor would compromise the performance or reliability of the ADF4106.

2)  Given the PLL parameters that I have listed above, such as setting a 10 nsec Digital Lock Winodw, waiting 3 or 5 consecutive phase detector cycles, the PLL/VCO locking within 50usec which is a function of the loop filter bandwidth, and PFD frequency (not defined) can you find any reason why we cannot directly interface a CMOS VHDL device to the ADF4106 Digital Lock Detect signal?

  • 0
    •  Analog Employees 
    on Oct 2, 2009 12:44 AM

    Hi Tim,

    Yes you can drive a CMOS load but only if you remove the 1 uF capacitor.

    The ACCURACY of the digital lock detect is a function of the PFD frequency; the higher the frequency, the higher the error.

    (The state machine looks for the periods of the two inputs to the PFD to be within a few ns of each other, but the higher the PFD input frequency, the shorter the period of the two inputs. At 100 MHz, which is possible with the ADF4160, the two periods are going to be roughly 10 ns, so even a 10% frequency error would put the two periods within 1 ns of each other and cause a LOCK output.)

    Regards,

    Bob

  • 0
    •  Analog Employees 
    on Oct 2, 2009 2:02 AM

    The output of the Digital Lock Detect is feeding a 3.3v LDO to isolate the MUXOUT pin from their noisy FPGA.  There is a 1uF cap on the input of the LDO.

    Will directly interfacing the Digital Lock Detect to the FPGA cause performance issues.  I'm concerned that the noisy FPGA will inject noise back into the MUXOUT pin and cause performance (phase noise) issues with the 4106.  The LDO circuit was there to help isolate and prevent noise from getting back in.

    In that same vein, I'm concerned that a 1uF cap, during a power down, will inject charge/current back into the MUXOUT pin and cause some cumulative damage.

  • 0
    •  Analog Employees 
    on Oct 2, 2009 4:03 AM

    Hi Tim,

    You're right! The capacitor should go as should the LDO. It would be safer to use either an op amp or a comparator like the ADCMP600 to isolate the FPGA. The ADCMP600 has a R-R input so it can be tied directly to the MUXOUT as a buffer. It's output is NPN/PNP collectors tied together so reverse isolation should be decent.

    Regards,

    Bob

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:08 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin