AGC control loop using AD8362 in controller mode.

Do you have any information on the Gain Control Bandwidth of the AD8362's output op-amp? I want to use the AD8362 in Controller Mode and want to factor this bandwidth into my loop calculations.

  • The AD8362 op amp was not characterized when the device was being prepared for release. The main reason for this stems from the fact that the required rms averaging (i.e. the cap on CLPF) tends to dominate the response time of the circuit. If you made CLPF so small that the bandwidth of the op-amp comes into play, then you are probably not doing a valid rms computation, or to put it another way, the device will be giving you the wrong answer. This means that there is little justification for using an rms device. If speed is a concern and rms does not matter, you would be better off using a non-rms device like AD8317/8/9.
    Using the attached plot from the AD8362 datasheet, we could make some very rough calculations of output bw. The rise time of this pulse is around 100 ns (hard to tell because of the scale). The nasty settling is the internal rms loop settling so don't worry about that.  So if you do a (1/(2xPIx100ns) calculation, you get  1.6 MHz.  From this result, the best we can say is that the op-amp has a unity gain bw of at least this number and probably a fair bit more than this.
    It is worth mentioning that the Controller Mode on the AD8362 (or any of the rf detectors for that matter) is not used that much. One concern I have about running a device like this in controller mode is that  any residual noise that is not removed by CLPF (CLPF is now the core of the current driven error integrator) will be modulated onto the carrier via the gain control line of the VGA or VVA that is being controlled.  To make the AD8362's Vout very quiet, CLPF will have to be very large which will give you a very sluggish loop. 
    To study this more closely, you would need to to do the following experiment. Apply a very clean sine wave (very low phase noise in the 10KHz to 10 MHz range) and/or a modulated carrier with low acpr,  into a VGA/VVA that is being controlled by by an AD8362. Then you start varying the size of CLPF and look for signs of phase noise degradation (sine wave) or ACP degradation (in the case of the  modulated carrier). Once you have found a CLPF big enough to give no signal degradation, you check out the step response time and see if it is acceptable.
    You should probably have to look at EVM degradation in addition to ACP degradation as a measure of circuit performance. Gain pumping is yet another effect you need to be careful to avoid. If the loop is agile (small CLPF), then instantaneous power changes on the input signal (as the envelope power  varies),  may cause the control loop to falsely respond and "pump" the gain control voltage in an effort to flatten out the envelope.
    Performing this test with just a sine wave may give deceptively good results because performing an rms computation on a sine wave (mixing it with itself), generates a nice dc voltage with no noise. However, if you mix a QAM carrier, with itself, you get a mess of noise down at dc.