Can you sugest me a clock spliter chip to drive three PLL REF with one CMOS output tcxo?
Because the REFIN pin on the ADF4xxx PLLs are high impedance (> 10kOhm) you should be able to simply ac-couple the signal into the 3 REFin pins using 3 capacitors. We also have dedicated fan-out buffers like the ADCLK914 (1:4 fan-out) but these are more suited/useful for high frequency signals
But I have to use the OCXO as a 10MHz reference output besides the three PLL ref,the OCXO can't have enough drive to do this.could you give me annother sulotions? I consider using a SN74HCT chip ,but I don't konw what their additive phase noise are.
Here is a circuit we have used on some ADI boards to distribute a 10MHz clock like you mentioned.
the idea is to bias the VCTCXO/OCXO output (ac-coupled) at midsupply and then send it through two inverters. The second inverter is necessary to present the falling edge of the VCTXO to the PLL as the PLL samples off the negative edge internally. For a VCTCXO the least noisy edge is the falling one. By only having one inverter, you would be presenting the noisier VCTCXO rising edge to the PLL. I think for the OCXO you could use just one inverter as both edges should be clean. However I think a dual inverter should also be quite cheap.
We routed the REFIN_SHIFT net around the board, and had the pair of inverters at each PLL input, so this idea
could easily be extended to more than 3 PLLs