I used adf4360-0 to synthesize a 2.5GHz clock, but the clock can not lock. the schematic, ADISimPLL simulation file and register configuration values are attached.
The 3-wire interface is controlled by a FPGA, and the interval between the control latch and N counter latch is about 15ms.
will somebody give me some opinions about the problem here. thanks sincerely.
note: there is an error in the schematic, the AVDD, DVDD and VCCO are derived from a "VCC3V3A1" which is generated by a LT1761(max output current is 100mA) and there are serial capacitances between them and the "VCC3V3A1", so i solder 0R resistances instead.
