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ADF4156 phase resync

ADF4156 Phase Resync Operation

I am having a problem that the output phase can only keep its relation to
the ref phase for about one minute after phase resync operation. How can I
make sure the phase relation is matched all the time? I followed the
calculation on the datasheet. It seems to be it only talk about the shortest
time I can sync the phase. It is true that once I done phase resync during
startup the phase relation should always be kept? I

  • Once you program the device even with phase resync disabled the output phase should stay constant unless you change frequency or re-write

    to the registers. You need to ensure this before you can go on to testing the phase reysnc functionality.

    How are you measuring PLL output phase ? If on a modulation domain or vector network analyser make sure the ADF4156 reference and the

    instrument are frequency synhronised. the simplest way to do this is to use the 10MHz reference output as the reference in for your ADF4156.

    you should bypass the on-board TCXO in this case.

    When phase resync is enabled it ensures that the phase is kept constant on each channel even when you hop to another frequency and then

    return back to the original frequency.

    Do a search for 'ADF4350 phase resync' on this forum for a document I wrote on phase resync using the ADF4350 which will give you some

    more detail.

  • Hi Austin

    In my system the ADF4156s share the same 10MHz reference but they are not initialized simultaneously. Is it still possible for me to control all the PLLs to give equal phase output?

    If I give up the fractional function of ADF4156 by setting the "fractional value" to zero, will the phase output behaves like a normal interger N PLL?

  • If the ADF4156's are not initialised simultaneoulsy, then they will potentially power up on different phases.

    You would need some method to calibrate out the initial phase difference.

    You could use the ADF4156 as an integer-N PLL by setting the frac word to zero. In this case the phase

    resync becomes much simpler. The simplest way to achieve phase resync for integer-N PLLs is to hold

    all devices in couter reset after power-up and release the reset simultaneously by means of a shared

    SPI LE line. Check the following article for some more detail on this.

    http://www2.electronicproducts.com/Selecting_PLLs_for_timing_and_phase_control-article-analog-feb2006-html.aspx

  • Thanks Austin

    I have another question about phase sync for ADF integer N PLL. If the chips are required to initialised or enable simultaneoulsy to achieve zero phase different, does it mean the ADF integer N PLLs can only track reference frequency but not reference phase?

    I am also working on a carrier recovery circuit in which phase tracking is required. The Ref pin is used as the input of the circuit so the VCO can automatically track the input frequency and phase. Are ADF integer N PLLs capable for this?

  • the ADF4xxx PLLs do track phase - the problem is that the Reference divider and feedback divider (N-Div) introduce uncertainty as

    to which edge the divided output will appear on. That is why you need to apply a simultaneous counter reset - so that all devices

    counters start at the same time.

    For a carrier recovery loop the ADF PLLs will actively track phase.  ADIsimPLL allows you to calculate the PLL rms phase jitter

    with a carrier recovery loop. Do a search for carrier recovery in the ADsimPLL help.

  • Hi Austin

    Sorry, I think I have not been explaining my concern properly.

    For this AM demodulator, the PLL phase output has to in phase to the AM input for coherent detection.

    For Interger N ADF4XXX PLLs, what have to be done to make sure the AM signal phase and PLL phase are always in phase?

  • ok thanks for the block diagram - I think in this case if the Reference divider = 1, then you should get close to zero phase difference

    between RFout and REfin. There is a finite propagation delay through the divider chain which will cause an offset, this is in the order

    of a few hundred ps according to Ian Collin's article I pasted the link for above. This might be acceptable depending on the carrier frequency.

    If R is not equal to 1, then I think the phase could appear at any +/- 360deg/R intervals depending on which edge of the reference the divider

    starts counting. You should draw out the signal timing for the case where R=2 and N=3, you will see that there are two possible phases the

    RF output will have relative to the reference.

    What is the carrier frequency in this case ? There might be a more suitable part than the ADF4156 that would allow R=1.