ADL5375 output power

I'm now testing AD9779A-DPG2-EBZ evaluation board.

It has TxDAC AD9779A and IQ-modulator ADL5375-05 onboard.

Modulation data stream is generated from external FPGA and LO input comes from ADF4350-EB1Z.

Generated RF spectrum works as expected, but output power level seems lower than the value

in ADL5375 datasheet as LO frequency goes higher.

Measured values are as follows;

0dBm @750MHz

-3dBm @2GHz

-6dBm @3.65GHz

ADL5375 datasheet says Pout is between 0dBm and 1dBm in frequency range 0.45-3.5GHz.

I suppose Viq level is tuned in the evaluation board, and LO level from ADF4350-EB1Z is in appropriate level.

Any comments on the cause of loss and methods to improve S/N are highly appreciated.

Takashi

  • 0
    •  Analog Employees 
    on Feb 6, 2012 6:34 PM

    The LO level for the ADF4350 PLL has little or no effect on the IQ Modulator output power. You need to look at the voltage swing from the DAC to see if you are getting the right IQ Modulator ouptut level. There are two tools available that allow you to the level planning.  There is an FAQ that contains a DAC-Modulator spreadsheet calculator

    http://ez.analog.com/docs/DOC-1271

    or you can use the ADIsimRF tool which allows more basic calculations to be made.

    www.analog.com/adisimrf

  • Dear enash,

    Thanks for your reply. The calculator seems useful.

    But my question is output power dependency on LO frequency, not LO level.

    Check the spectra below. These were measured on the same conditions except for LO frequencies.

    I wonder why this happens, since ADL5375 datasheet says output power is almost flat regardless of LO frequency.

    As for IQ swing voltage, I suppose correct load is already set to achieve optimal 1Vp-p in the evaluation board, isn't it?

    ADL5375 datasheet and CircuitNote CN-0021 recommends 100ohm as RL, but AD9779A-DPG2-EBZ (Rev.D) actually uses 140ohm (R15,16). This is another question.

  • 0
    •  Analog Employees 
    on Feb 7, 2012 7:32 PM

    My apologies. I misunderstood. If I'm reading your plots correctly, you are seeing a difference in power between 750 MHz and 3.5 GHz of around 6-7 dB. That does seem much larger than it should be.  Some of the loss will be due to the trace length from the output of the IQ Modulator to the SMA connector. Also your cable will have increased insertion loss at the higher frequency (you may have calibrated out your cable losses; I can't tell).

    There is nothing particularly special about the 1Vpp drive level. It's really just a nominal drive level that we use to calculated the gain of the IQ modulator.  With a modulated carrier, we typically find that the peaks of the signal should probably be a bit below 1V pp. However this is something you need to decide. Higher pp drive gives you more signal and more distortion; lower drive gives improved distortion but poorer SNR.

    The differential DAC outputs are currents so the resistive loading that is presented (in the form of two 50 ohm resistors to ground and a single shunt resistor) determines the drive voltage to the IQ modulator. Increasing the shunt resistor to 140 ohms therfore increases the drive level. This can also be simulated in the Excel calculator.  In a real transmitter, the DAC anti-aliasing filter is typically placed between the 50 ohm resistors and the single shunt resistor. So for the case above, you would need to design a filter that expects to see a source impedance of 100 ohms (i.e. 2 times 50) and a load of 140 ohms. This is not a big deal for a typical filter design program.

  • Dear enash,

    Thanks for the exposition on IQ input level. Now I understand better.

    As for modulator output loss, I wonder why the loss is thus big.

    (Cable loss is 0.4dB at 4GHz, so almost negligible here)

    AD9779A-DPG2-EBZ uses RO4350B and impedance controlled coplaner waveguide, and line length is only 10mm.

    What I felt odd was the transmission line plane is changed from top to bottom layer right after ADL5375 output pin through via, which seemed unnecessary to me.

    Any advice in designing PCB layout to minimize loss?

  • 0
    •  Analog Employees 
    on Feb 8, 2012 7:02 AM

    Routing RF traces through vias is not optimal and is best avoided but should not give a bunch of loss. If you can, set up the DAC to put out a sinewave at, say, 1 MHz. Probe the voltage at the modulator's diff-in pins and see if you can measure the gain of the device to compare to the datasheet spec.