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Failure Analysis of Burned ADF4153 & ADF4106

Dear all,

we have recently experienced a number of return of synthesizers build with ADF4153 and ADF4106.

These circuits use 2 supplies of +5V (VCO and PLL) supply and 15-20V (Vtune).

The PLL supply of 3.3V comes from the +5V through a low noise regulator. The VP is tied to +5V of VCO.

The charge-pump pin 20 is connected to the negative input of an OpAmp (used as integrator for the PLL filter).

The OpAmp supply is 15-20V to GND.

All these cases exhibit low impedance on the charge-pump pin (Pin 20).

I have removed (un-soldered) the ADF4153 from the PCB and I checked the impedance with a multimeter (set for diode/continuity measurement).

The following is the result of the measurement:

Measurement Returned ADF4153
Good ADF4153
CP (pin20) -> GND 28 Ohm Open
GND -> CP (pin20) 28 Ohm 0.569V (ESD diode)
Vp (Pin18) -> GND 1.5V Open
GND -> VP (Pin18) 0.57V 0.565V
Rset (pin 19)-> GND 2.01V Open
GND-> RSET (pin 19) 0.585V 0.569V

Please note that the 28Ohm impedance to ground was observed also when the ADF4153 was soldered on PCB. The good-working PCBs do not exhibit this short.

The answer to the following question will be appreciated:

Q1. In your opinion, what could cause such behavior?

Q2. Is it possible to investigate the failure on the damaged device?

Q3. What FIB houses could provide such investigation?

Q4. How much would cost the failure investigation ?

Best regards,

Dorin

Parents
  • Dear Grzegorz,

    Thanks for providing the previous helpful answer.

    We are trying to perform an exhaustive failure analysis (in the limits of practicality).

    I am including a pseudo-netlist of the PLL loop filter.

    Could you respond if with such filter the supply sequence could cause a damage of the Charge Pump pin?

    Also, if I replace the ADF4106 with ADF4153, would I achieve the same answer?

    (I need a second opinion/expertise)

    In short, the Charge-pump pin is provided to the negative input of the AD8671, used as integrator in a PLL loop filter. The PLL IC is biased by a 3.3V regulator, except the VP which is tied to 5V supply.

    The Opamp is powered by a 15V supply, while the V+ is biased to ~3V with a resistive divider from the 3.3V regulator.

    PLL_IC      ADF4106     18    19    17    0     20

    Op_AMP_IC   AD8671      1     20    99    0     39

    LDO_IC      LDO         18    0     17

    * the LDO (low drop-out regulator) provides 3.3V supply to PLL from 5V

     

    V1    18    0     5V

    V2    99    0     15V

     

    R1    19    0     4.7k        // RSET for PLL IC

    C1    1     2     100pF       // between Opamp V+ and V-

    C2    39    2     100pF       // between Opamp out and V-

    C3    39    38    1uF         // loop filter capacitor (Integrator Opamp)

    R3    38    2     10k         // loop filter resistor

     

    * OpAmp V+ bias below

    R4    1     0     51k

    R5    17    1     4.7k

    C5    1     0     1uF

     

    * subcircuits below

     

    * Node assignments ADF4106  only relevant pins shown

    *                       Charge Pump supply VP (pin 18)

    *                       |    RSET (pin 19)

    *                       |    |    positive supply (pin 17)

    *                       |    |     |     Ground  (pin 8)

    *                      |    |     |     |   Charge Pump output (pin 20)

    *                      |    |     |     |      |

    .SUBCKT ADF4153       18    19    17    0     20

    .ENDS ADF4153

     

     

    * Node assignments LDO

    *                       positive supply 5V

    *                       |     Ground

    *                      |    |     3.3V output

    *                       |    |     |   

    .SUBCKT ADF4153         18    0    17   

     

    .ENDS ADF4153

    * Node assignments AD8671       

    *                       non-inverting input

    *                       |    inverting input

    *                       |    |    positive supply

    *                       |    |     |     negative supply (GND)

    *                      |    |     |     |   output

    *                      |    |     |     |      |

    .SUBCKT AD8671         1    2     99    0     39

    .ENDS AD8671

     

     

Reply
  • Dear Grzegorz,

    Thanks for providing the previous helpful answer.

    We are trying to perform an exhaustive failure analysis (in the limits of practicality).

    I am including a pseudo-netlist of the PLL loop filter.

    Could you respond if with such filter the supply sequence could cause a damage of the Charge Pump pin?

    Also, if I replace the ADF4106 with ADF4153, would I achieve the same answer?

    (I need a second opinion/expertise)

    In short, the Charge-pump pin is provided to the negative input of the AD8671, used as integrator in a PLL loop filter. The PLL IC is biased by a 3.3V regulator, except the VP which is tied to 5V supply.

    The Opamp is powered by a 15V supply, while the V+ is biased to ~3V with a resistive divider from the 3.3V regulator.

    PLL_IC      ADF4106     18    19    17    0     20

    Op_AMP_IC   AD8671      1     20    99    0     39

    LDO_IC      LDO         18    0     17

    * the LDO (low drop-out regulator) provides 3.3V supply to PLL from 5V

     

    V1    18    0     5V

    V2    99    0     15V

     

    R1    19    0     4.7k        // RSET for PLL IC

    C1    1     2     100pF       // between Opamp V+ and V-

    C2    39    2     100pF       // between Opamp out and V-

    C3    39    38    1uF         // loop filter capacitor (Integrator Opamp)

    R3    38    2     10k         // loop filter resistor

     

    * OpAmp V+ bias below

    R4    1     0     51k

    R5    17    1     4.7k

    C5    1     0     1uF

     

    * subcircuits below

     

    * Node assignments ADF4106  only relevant pins shown

    *                       Charge Pump supply VP (pin 18)

    *                       |    RSET (pin 19)

    *                       |    |    positive supply (pin 17)

    *                       |    |     |     Ground  (pin 8)

    *                      |    |     |     |   Charge Pump output (pin 20)

    *                      |    |     |     |      |

    .SUBCKT ADF4153       18    19    17    0     20

    .ENDS ADF4153

     

     

    * Node assignments LDO

    *                       positive supply 5V

    *                       |     Ground

    *                      |    |     3.3V output

    *                       |    |     |   

    .SUBCKT ADF4153         18    0    17   

     

    .ENDS ADF4153

    * Node assignments AD8671       

    *                       non-inverting input

    *                       |    inverting input

    *                       |    |    positive supply

    *                       |    |     |     negative supply (GND)

    *                      |    |     |     |   output

    *                      |    |     |     |      |

    .SUBCKT AD8671         1    2     99    0     39

    .ENDS AD8671

     

     

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