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ADF4212L power up sequence through rate

Hi,

As a local distributor, our customer is facing to error when starting up ADF4212L. By studying in the customer's side, they found VDD1=VDD2=3.3V might be a cause when it relatively slow / long ramp-up period, as shown in below at yellow line indicates.

It seems there is no description defined in datasheet in regard to power up, so if you provide required specification how long, how fast, how steep or any to achieve normal start up of this PLL device. Other words, the customer may be able to see good result when shorten above ramp-up period, but feeling needs to confirm what is defined power up sequences.

Any of your comments or supports would be very much appreciated.

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  • Hi,

    a) The test mode is a special mode of work which is built into the part and which allows to test proper functionality of different internal blocks of the part. However, it is for ADI internal usage and generally we do not provide any documentation of the test modes for the customers, as the way they should use the part does not involve the test mode.

    b) One of the possible reasons for the part powering up at test mode may be some ringing signal on rogramming interface (LE, DATA, CLK) which may accidentally write not allowed value to reserved fields of the registers. If the power supply slew rate is very slow, the internal registers may start to accept the state from the programming lines before the supply reachs the final value 3 V, especially if these lines are connected to some other logic device that may behave unstable during power up.

    Unfortunately i do not know what is connected to programming interface lines in your's customer's circuit and they may need to investigate if this part that drives LE, CLOCK and DATA lines is stable during the supply power-up wih slow slew rate.

    Regards

Reply
  • Hi,

    a) The test mode is a special mode of work which is built into the part and which allows to test proper functionality of different internal blocks of the part. However, it is for ADI internal usage and generally we do not provide any documentation of the test modes for the customers, as the way they should use the part does not involve the test mode.

    b) One of the possible reasons for the part powering up at test mode may be some ringing signal on rogramming interface (LE, DATA, CLK) which may accidentally write not allowed value to reserved fields of the registers. If the power supply slew rate is very slow, the internal registers may start to accept the state from the programming lines before the supply reachs the final value 3 V, especially if these lines are connected to some other logic device that may behave unstable during power up.

    Unfortunately i do not know what is connected to programming interface lines in your's customer's circuit and they may need to investigate if this part that drives LE, CLOCK and DATA lines is stable during the supply power-up wih slow slew rate.

    Regards

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