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ADF4212L power up sequence through rate

Hi,

As a local distributor, our customer is facing to error when starting up ADF4212L. By studying in the customer's side, they found VDD1=VDD2=3.3V might be a cause when it relatively slow / long ramp-up period, as shown in below at yellow line indicates.

It seems there is no description defined in datasheet in regard to power up, so if you provide required specification how long, how fast, how steep or any to achieve normal start up of this PLL device. Other words, the customer may be able to see good result when shorten above ramp-up period, but feeling needs to confirm what is defined power up sequences.

Any of your comments or supports would be very much appreciated.

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  • Hi,

    We have not seen so far any case of the ADF4212L  working improperly due to different speed of power supply rising from 0 to 5 V, and we do not have any specification on timing for switching on power supply.

    As you described the error, the CPout stays at 5 V all the time - it may indicate that when the part is powered up, it may wake up in some test mode - in this case, it will stay in this test mode even when you send some other register value, until you clear the test mode - to do so, it is necessary to clear all bits (programm them to 0) in Register 0 (IF R counter latch) and write 0x2 to Register 2 (clear all bits except the control bits in RF R counter latch), and only after that is done, the part may be programmed properly.

    Please let me know if this solution works for the customer.

    Best regards

Reply
  • Hi,

    We have not seen so far any case of the ADF4212L  working improperly due to different speed of power supply rising from 0 to 5 V, and we do not have any specification on timing for switching on power supply.

    As you described the error, the CPout stays at 5 V all the time - it may indicate that when the part is powered up, it may wake up in some test mode - in this case, it will stay in this test mode even when you send some other register value, until you clear the test mode - to do so, it is necessary to clear all bits (programm them to 0) in Register 0 (IF R counter latch) and write 0x2 to Register 2 (clear all bits except the control bits in RF R counter latch), and only after that is done, the part may be programmed properly.

    Please let me know if this solution works for the customer.

    Best regards

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