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ADF4212L power up sequence through rate


As a local distributor, our customer is facing to error when starting up ADF4212L. By studying in the customer's side, they found VDD1=VDD2=3.3V might be a cause when it relatively slow / long ramp-up period, as shown in below at yellow line indicates.

It seems there is no description defined in datasheet in regard to power up, so if you provide required specification how long, how fast, how steep or any to achieve normal start up of this PLL device. Other words, the customer may be able to see good result when shorten above ramp-up period, but feeling needs to confirm what is defined power up sequences.

Any of your comments or supports would be very much appreciated.

  • Hello,

    We need more information to figure out what may be the reason for the issue that the customer is experiencing. You mentioned that the customer face an error - but unfortunetely we don't know what this error is, neither if it is on RF channel or IF channel, as there is no explanation what this error looks like. I would appreciate if you could provide some more detailed information so that we could investigate this case.

    As a first-hand advice, i would like to ask you to clear all bits (programm to 0) in Register 0 (IF R counter latch) and write 0x2 to Register 2 (RF R counter latch) after the part is powered up, and only after that is done to write all you register with current settings. Does the error still appear after this sequence? And what is the error?

  • Hi Grzegorz Wawrzola,


    Thank you very much for your reply and sorry for my shortage. I understand

    your point what type of error is key to care.

    However, the first question of the customer is quite simple that,


    Does ADF4212L have any specification of power up sequence/timing ? If it

    has, please provide.


    The customer has experienced to use same device, ADF4212L, on existing

    products without any problem, and now try to adopt on another new products.

    So, they are not amateur of this device and also other Analog Devices


    But their new products have different power supply, as I attached waveform,

    than previous products, and gets a error which PLL is not locked at IF side,

    after starting up.

    When it occurs, CP(charge pump) output stay and stuck to +5V, as same

    voltage as Vp1 and Vp2.

    They confirmed sending command from host MCU after power becoming

    suffuciently stable.

    Once ADF4212L becomes to be a state which is not locked, it can not be

    recovered even though resending host command again.

    Only the way to recover is, powering down on the device and power on again.

    Because it seems issue on starting of ADF4212L, the customer doubt their

    power supply may be out of specification.


    The customer can not recreate this issue at all times. They say it sometimes


    As I wrote before, when trying to make this power ramp-up period more short,

    they feel it becomes to be improved,

    however, because they can NOT recreate the issue everytime, they need to

    confirm the specification of starting power supply on ADF4212L.

    This is reason why of their question.


    Best Regards.

  • Hi,

    We have not seen so far any case of the ADF4212L  working improperly due to different speed of power supply rising from 0 to 5 V, and we do not have any specification on timing for switching on power supply.

    As you described the error, the CPout stays at 5 V all the time - it may indicate that when the part is powered up, it may wake up in some test mode - in this case, it will stay in this test mode even when you send some other register value, until you clear the test mode - to do so, it is necessary to clear all bits (programm them to 0) in Register 0 (IF R counter latch) and write 0x2 to Register 2 (clear all bits except the control bits in RF R counter latch), and only after that is done, the part may be programmed properly.

    Please let me know if this solution works for the customer.

    Best regards

  • Dear Grzegorz,


    Even if problem situation is "test mode" and the customer can clear it for

    normal usage, I'm afraid this solution may not satisfy the customer.

    I have asked this to the customer, and now waiting for their input, however,

    meanwhile, could you please let us know,


    a) What is test mode, and what's the purpose of test mode at ADF4212L ?

    (Probebly it's only for ADI internal usage ?)

        I could not find out any technical documentation which is describing it.

    b) Can you see any possible reason/trigger why it goes into test mode, if it

    is ?


    Sorry to these basic questions, and appreciate you helps bringing to



    Best Regards,

  • Hi,

    a) The test mode is a special mode of work which is built into the part and which allows to test proper functionality of different internal blocks of the part. However, it is for ADI internal usage and generally we do not provide any documentation of the test modes for the customers, as the way they should use the part does not involve the test mode.

    b) One of the possible reasons for the part powering up at test mode may be some ringing signal on rogramming interface (LE, DATA, CLK) which may accidentally write not allowed value to reserved fields of the registers. If the power supply slew rate is very slow, the internal registers may start to accept the state from the programming lines before the supply reachs the final value 3 V, especially if these lines are connected to some other logic device that may behave unstable during power up.

    Unfortunately i do not know what is connected to programming interface lines in your's customer's circuit and they may need to investigate if this part that drives LE, CLOCK and DATA lines is stable during the supply power-up wih slow slew rate.