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ADF4158 PLL strange 'moving' spurs

Hi there,

I've made a PLL design going from 900 to 1000 Mhz using the ADF4158 and I'm experiencing strange results.

The VCO is Minicircuit ROS-1000V (850-1050 Mhz), the loop filter is an active inverting low noise opamp (OP184). Components values from ADIsimPLL

When generating 890 000 000 Hz with no modulation, I see my carrier and two side carriers at +/-315 KHz and -65dB approx.

But what is strange, I see two other carriers which are moving quite fastly, symetrically at each side of the main carrier and going into opposite direction like if it was starting from the carrier, and one is going down in frequency whereas the second is going high... and then it's comes back and return and so on...

Replacing the REFin from a TCXO (with multiple harmonics) to an externa DDS function generator doesn"t change anything.

If I change the frequency setting to for instance 890 000 005 Hz I change the speed of these moving carriers. If  I set 890 001 250, there is no longer these carriers.

The power supply is supposed to be quite clean and nothing serious appears on the oscilloscope (noise of about 2-5mV in x1 probe). On each RF device there are 2 X7R caps (10pf, 100nF) following a bead ferrite. PCB layout has proper grounding.

On the same board I have a CPU running at 18.668 MHz from a 4.9152 MHz crystal and I'm wondering if these carriers could be a beat frequency from a mixing between any of the CPU clocks and the PLL. Does anyone has heard about a such thing ?

Does anyone has already experienced a such behaviors on these 'moving' spurs. Any idea on how to investigate ?




  • I'm sure this would work. But then how to detect problematic frequencies.... mmmm, not sure a such solution is a great approach. If we are at that point, I guess it means an other PLL chip or technology should be considered.

    I still don't understand what is the impact of CP and bleed current settings on spurs and phase noise. This is not documented in the datasheet. And I still don't understand why the phase noise I get is so far from the ADISimpPLL simulation results (15 to 20 dB off for phase noise @ 10 kHz).

    If what I measure is the nominal performance of that PLL chip, I'm quite disapointed as it's far from what the datasheet specifies and from my applications requirements. In fact, I don"t see any application which could deal with such performances. There is apparently no setting which works for all frequencies. I had in mind initially to test the ADF4159 for the application we are targetting, but I guess I'll directly try something else.


  • It's pretty easy to work out the problematic frequencies. The 'moving' spur appears near the integer boundaries, so you could use a look-up table/algorithm to switch the PFD frequency when the desired output frequency is within 200 kHz of the integer boundary.

    For example, if your desired frequency is 950.1 MHz; this is 100 kHz from the 950 MHz boundary, so you could then switch the PFD frequency to 6.66 MHz. This would move the integer boundaries to 945.72 MHz and 952.38 MHz so the output would not be affected by the moving spur.

    You could then use the charge pump current to maintain a constant loop filter bandwidth (LBW). If your LBW is 100 kHz with CP = 2.5 mA and PFD = 10 MHz; you can keep the 100 kHz LBW at PFD = 6.66 MHz by changing the CP to 3.75 mA. ADIsimPLL will do this for you - I can show you in more detail if required.

    I think there may be too may variables in your system to make the bleed current a viable option.

    Regardless of whether you are using the bleed currents, the measured results shouldn't be 15 to 20 dB away from the simulated results - are you sure your set up matches the ADIsimPLL simulation parameters? Are you simulating the noise parameters of your active loop filter op-amp?

  • This is an interresting strategy indeed to limit spurs around the integer values. It might indeed push the spurs to an acceptable level.

    For the 15-20dB phase noise issue, my design is actually done like described in the ADIsimPLL porject I've attached above. The VCO is a minicircuit ROS1000V which is the one selected in the project and the active loop filter is using an OP184 opamp in the configuration given in the ADIsimPLL project. So I guess my design is really very close from the ADISimPLL project simulation. The only thing is that the opamp is supplied with an asymetrical power supply

    I had a doubt on power supplies and the REFin. This is always easy to make mistalkes. I've for instance noticed that the TCXO has a lot of harmonics which I haven't filtered. So I tried 3 different sources for 10 MHz REFin : the TCXO, a DDS function generator and a GPSDO this has not changed anything on phase noise or spurs.

    I've then tried to check the OP184 power supply which comes from a charge pump in my design. I tried to replaced with an external clean power supply.which has not brought anythins special as well. The other power supplies are clean.

    From what I've seen, CP and BLEED_CURRENT settings have a high impact on phase noise. It can change easily by 20dB in the 100 Hz - 10 KHz range. I've havn't tested all the combinations, but the best one I've found for the moment is still providing a phase noise much higher than the -105dBc/Hz given in the simulation.

    However the loop filter is no longer computed for the selected CP value. I'm going to make the modification, choosing the best CP value (very likely 0.64 or 0.91mA) and then rework the loop filter accordingly.

    If it sounds strange for you as well that I do not reach the simulation phase noise, I'm going to investigate further... even If don't see what I can do more right now....

    What do you mean by "Are you simulating the noise parameters of your active loop filter op-amp". Is there anything special to do more than selecting an opamp ? At the moment the simulation gives a result for phase noise brought by the loop filter which is quite low. See attached


  • The R1 C1 low pass filter should have minimal effect on in-band noise - you can simulate this with ADIsimPLL.

    I'm still concerned about the vast difference between the ADIsimPLL phase noise predictions and your results. As they are way off in-band, have you eliminated reference noise as a possibility, do you have a clean reference and are you meeting the slew rate requirement on the reference input?

  • The spurs reduction near integer boundaries can't work for all values. For instance for any multiple of 20e6 Hz there is no combination of doubler, divider and R that enables having fractional part. Any suggestion ?

    For the loop filter, I'm going to try. What is the effect of this first low pass filter of 3 MHz to the in-band noise ?

  • Is it possible to avoid using the frequencies at multiplies of 20 MHz? Or try building a look-up table of optimum charge pump current with negative bleed enabled at 900, 920, 940, 960, 980 and 1000 MHz?

  • no way to avoid any frequency as I'm building a versatile LO block that can be used in differents applications.

    So yes I can improve with strategies to limit as possible unwanted effects. This might be the only compromise we can do at some point, right ?

    I'm working on the loop filter at the moment. I'll come back when I'll get results.



  • For the reference I'm using a 10 MHz TCXO from Connor-Winfield (D75A). It has a LVCMOS output with about 2.5ns/v slew rate but harmonics every 10 MHz up to GHz ! The design allows an external reference to be used via a splitter between the TCXO which can be disabled and the external reference.

    I've then tried to used a DDS based function generator from Stanford Research (DS345) both with sine and squarre output as well as a GPS disciplined OCXO from HP (HP58503B)

    These 4 configurations have not changed significantly the phase noise and the TCXO (green) with the GPS (red) provides the best values.

    The phase noise plot is automated thanks for the GPIB toolkit freeware that just controls the HP8562E. Even without the automated acquisition, I can see the noise on the carrier feet which is far above the HP8562E noise floor. I've no other mean to validate the measurement itself but I'm quite confident on the measurement result.

    I've checked power supplies on which efforts have been brought to ensure low noise. (ADP3300 and ADP3331 + bead inductors and capacitors on each RF component. Remaining noise is < 5mV.

    I'm going now to modify the loop filter according your comments.

  • There is something strange here:

    - in the plot above the 20kHz loop appears to have a wider LBW than the 100kHz loop

    - as well as the in-band noise disagreeing with simulations, the SDM noise predicted by ADIsimPLL is nowhere to be seen

    It's very hard to diagnose at a distance, but you have to eliminate each possible source of the noise, and the ones that come to mind are:

    1. Reference noise - have you measured the phase noise of the reference (or possibly - for more sensitivity, a harmonic) and verified that the in-band noise is not just multiplied reference noise?

    2. Have you met the input slew-rate requirement on the reference input?

    3. Is the power supply to the chip clean (some 3 terminal regulators can put out lots of low frequency noise)? Low frequency noise on the power supply can appear as phase noise by modulating the logic switching levels.

    4. Is the reference supply to the op-amp non-inverting pin clean? (note: loop tends to reject this noise)

    5. carefully check the loop filter - VCO signal path and verify that no ground currents allow low-frequency noise injection (note: again the loop tends to reject noise from this source)

    6. Run at an integer-N frequency for a comparison. (isolates noise from SDM)

    7. Check noise on power supply to VCO.

  • I've modified the loop filter to match the CP value and I've tested two different loop filters values according ADIsimPLL configuration :

    - CP=5mA, BW = 20 KHz, Phase margin = 45°

    - CP=0.31mA, BW = 20 KHz, Phase margin = 45°

    In both cases, I still have the inband phase noise more than 10dB above the simulation

    Now I'm stuck. No ideay where to investigate these inband 10dB difference

    I'm going to test a second prototype with an other VCO running at an other frequency and check if again I'm not getting the simulation performances.