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ADF4158 PLL strange 'moving' spurs

Hi there,

I've made a PLL design going from 900 to 1000 Mhz using the ADF4158 and I'm experiencing strange results.

The VCO is Minicircuit ROS-1000V (850-1050 Mhz), the loop filter is an active inverting low noise opamp (OP184). Components values from ADIsimPLL

When generating 890 000 000 Hz with no modulation, I see my carrier and two side carriers at +/-315 KHz and -65dB approx.

But what is strange, I see two other carriers which are moving quite fastly, symetrically at each side of the main carrier and going into opposite direction like if it was starting from the carrier, and one is going down in frequency whereas the second is going high... and then it's comes back and return and so on...

Replacing the REFin from a TCXO (with multiple harmonics) to an externa DDS function generator doesn"t change anything.

If I change the frequency setting to for instance 890 000 005 Hz I change the speed of these moving carriers. If  I set 890 001 250, there is no longer these carriers.

The power supply is supposed to be quite clean and nothing serious appears on the oscilloscope (noise of about 2-5mV in x1 probe). On each RF device there are 2 X7R caps (10pf, 100nF) following a bead ferrite. PCB layout has proper grounding.

On the same board I have a CPU running at 18.668 MHz from a 4.9152 MHz crystal and I'm wondering if these carriers could be a beat frequency from a mixing between any of the CPU clocks and the PLL. Does anyone has heard about a such thing ?

Does anyone has already experienced a such behaviors on these 'moving' spurs. Any idea on how to investigate ?

Thanks

Regards

Stephane

Parents
  • Hi,

    Enabling the negative bleed current has improved but not enough. I haven't yet changed the CP as it requires to change the loop filter components also right ? I'll try next week.

    Regarding the noise floor, I'm surprised to see that there is no much difference between interger PLL and fractionnal PLL. You're talking about -223dBc/Hz whereas the ADF4158 exhibit -216 dBc/Hz... However 12-bits might be not enough for what I intend but I will investigate further on the ADF portfolio and probably try some other chips.

    I'll try adjusting CP and will let you know if it improves significantly or not.

    Thanks

    Stephane

Reply
  • Hi,

    Enabling the negative bleed current has improved but not enough. I haven't yet changed the CP as it requires to change the loop filter components also right ? I'll try next week.

    Regarding the noise floor, I'm surprised to see that there is no much difference between interger PLL and fractionnal PLL. You're talking about -223dBc/Hz whereas the ADF4158 exhibit -216 dBc/Hz... However 12-bits might be not enough for what I intend but I will investigate further on the ADF portfolio and probably try some other chips.

    I'll try adjusting CP and will let you know if it improves significantly or not.

    Thanks

    Stephane

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