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ADF4158 PLL strange 'moving' spurs

Hi there,

I've made a PLL design going from 900 to 1000 Mhz using the ADF4158 and I'm experiencing strange results.

The VCO is Minicircuit ROS-1000V (850-1050 Mhz), the loop filter is an active inverting low noise opamp (OP184). Components values from ADIsimPLL

When generating 890 000 000 Hz with no modulation, I see my carrier and two side carriers at +/-315 KHz and -65dB approx.

But what is strange, I see two other carriers which are moving quite fastly, symetrically at each side of the main carrier and going into opposite direction like if it was starting from the carrier, and one is going down in frequency whereas the second is going high... and then it's comes back and return and so on...

Replacing the REFin from a TCXO (with multiple harmonics) to an externa DDS function generator doesn"t change anything.

If I change the frequency setting to for instance 890 000 005 Hz I change the speed of these moving carriers. If  I set 890 001 250, there is no longer these carriers.

The power supply is supposed to be quite clean and nothing serious appears on the oscilloscope (noise of about 2-5mV in x1 probe). On each RF device there are 2 X7R caps (10pf, 100nF) following a bead ferrite. PCB layout has proper grounding.

On the same board I have a CPU running at 18.668 MHz from a 4.9152 MHz crystal and I'm wondering if these carriers could be a beat frequency from a mixing between any of the CPU clocks and the PLL. Does anyone has heard about a such thing ?

Does anyone has already experienced a such behaviors on these 'moving' spurs. Any idea on how to investigate ?

Thanks

Regards

Stephane

Parents
  • Thanks for your prompt answer.

    This is indeed apparently the problem.

    My PLL has a REFin of 10 MHz (TCXO), a 100 KHz loop filter with already a bias voltage of about 3V and CP=5mA

    Actually this effect is definitely undesirable for applications like RF receivers or instrumentation from my point of view and I need to get rid of that stuff. Possibly by choosing a PLL with a lower modulus like the ADF4157 but this brings then other problems. This suck a bit as I need to make a 12 GHz LO for an other application and the ADF4159 which is apparently the same than the ADF4158 but in 13 GHz version will exhibit the same 'problem'.

    Actually if there is no way to drastically improve this behavior I do not see any application where this could be acceptable meaning that this PLL is usable only at frequencies far from the PFD frequency multiples if I understand well. this is quite limiting and not clear from the datasheet reading.

    One thing made me confusing. I had a datasheet downloaded few months ago in revision B which doesn"t mention the NEG BLEED CURRENT setting in R4. It appears apparently in Rev C. The version currently available is Rev D but if you google ADF4158, the second link says Rev C whereas this is actuelly the Rev D which is downloaded. One learnt think, always get the datasheet from the manufacturer's website and not from a google link to the manufacturer's website....

    Now regarding the NEGATIVE BLEED CURRENT setting, I've turned the setting from 0 to 11 and this has increased the close phase noise which was already quite bad (-50dBm), This increased noise is masking a bit the moving carriers but they are still there with same level. The only benefit is that the close phase noise level doesn't change anymore when the 'moving' spurs are coming close to the carrier but it has degraded the overall phase noise apparently.

    I had already added a bias voltage on the inverting loop filter with a bridge resistor on the V+ of the OPAMP. This bias is about 3V (VCO tuning range is 12V).

    On the document you're mentionning I do not understand the table 1 on page 5 which shows some bleed % depending from the CP current. What shall we do with that ? Do I need to tune the bias on the filter according to the CP current ?

    My application is using CP=5mA. But I'm not sure I have as well understood the interrest of adjusting this CP to some other values as long as the loop filter is calculated in accordance.

    Thanks

    Stephane

Reply
  • Thanks for your prompt answer.

    This is indeed apparently the problem.

    My PLL has a REFin of 10 MHz (TCXO), a 100 KHz loop filter with already a bias voltage of about 3V and CP=5mA

    Actually this effect is definitely undesirable for applications like RF receivers or instrumentation from my point of view and I need to get rid of that stuff. Possibly by choosing a PLL with a lower modulus like the ADF4157 but this brings then other problems. This suck a bit as I need to make a 12 GHz LO for an other application and the ADF4159 which is apparently the same than the ADF4158 but in 13 GHz version will exhibit the same 'problem'.

    Actually if there is no way to drastically improve this behavior I do not see any application where this could be acceptable meaning that this PLL is usable only at frequencies far from the PFD frequency multiples if I understand well. this is quite limiting and not clear from the datasheet reading.

    One thing made me confusing. I had a datasheet downloaded few months ago in revision B which doesn"t mention the NEG BLEED CURRENT setting in R4. It appears apparently in Rev C. The version currently available is Rev D but if you google ADF4158, the second link says Rev C whereas this is actuelly the Rev D which is downloaded. One learnt think, always get the datasheet from the manufacturer's website and not from a google link to the manufacturer's website....

    Now regarding the NEGATIVE BLEED CURRENT setting, I've turned the setting from 0 to 11 and this has increased the close phase noise which was already quite bad (-50dBm), This increased noise is masking a bit the moving carriers but they are still there with same level. The only benefit is that the close phase noise level doesn't change anymore when the 'moving' spurs are coming close to the carrier but it has degraded the overall phase noise apparently.

    I had already added a bias voltage on the inverting loop filter with a bridge resistor on the V+ of the OPAMP. This bias is about 3V (VCO tuning range is 12V).

    On the document you're mentionning I do not understand the table 1 on page 5 which shows some bleed % depending from the CP current. What shall we do with that ? Do I need to tune the bias on the filter according to the CP current ?

    My application is using CP=5mA. But I'm not sure I have as well understood the interrest of adjusting this CP to some other values as long as the loop filter is calculated in accordance.

    Thanks

    Stephane

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