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ADF4158 PLL strange 'moving' spurs

Hi there,

I've made a PLL design going from 900 to 1000 Mhz using the ADF4158 and I'm experiencing strange results.

The VCO is Minicircuit ROS-1000V (850-1050 Mhz), the loop filter is an active inverting low noise opamp (OP184). Components values from ADIsimPLL

When generating 890 000 000 Hz with no modulation, I see my carrier and two side carriers at +/-315 KHz and -65dB approx.

But what is strange, I see two other carriers which are moving quite fastly, symetrically at each side of the main carrier and going into opposite direction like if it was starting from the carrier, and one is going down in frequency whereas the second is going high... and then it's comes back and return and so on...

Replacing the REFin from a TCXO (with multiple harmonics) to an externa DDS function generator doesn"t change anything.

If I change the frequency setting to for instance 890 000 005 Hz I change the speed of these moving carriers. If  I set 890 001 250, there is no longer these carriers.

The power supply is supposed to be quite clean and nothing serious appears on the oscilloscope (noise of about 2-5mV in x1 probe). On each RF device there are 2 X7R caps (10pf, 100nF) following a bead ferrite. PCB layout has proper grounding.

On the same board I have a CPU running at 18.668 MHz from a 4.9152 MHz crystal and I'm wondering if these carriers could be a beat frequency from a mixing between any of the CPU clocks and the PLL. Does anyone has heard about a such thing ?

Does anyone has already experienced a such behaviors on these 'moving' spurs. Any idea on how to investigate ?




  • The 'moving' spur is inherit to the high-order (25 bit) sigma-delta modulator. There are some steps you can take to reduce/remove the spur but most people have found it isn't actually a problem because the offset is always changing - i.e. no constant interference.

    The spur is worst near the integer boundary frequencies. This application note may help:

    You can also try changing the bias voltage on the positive input of your loop filter amplifier. The offset may push the charge pump into a region where the spur doesn't occur. This should just be a matter of replacing a resistor.

  • Thanks for your prompt answer.

    This is indeed apparently the problem.

    My PLL has a REFin of 10 MHz (TCXO), a 100 KHz loop filter with already a bias voltage of about 3V and CP=5mA

    Actually this effect is definitely undesirable for applications like RF receivers or instrumentation from my point of view and I need to get rid of that stuff. Possibly by choosing a PLL with a lower modulus like the ADF4157 but this brings then other problems. This suck a bit as I need to make a 12 GHz LO for an other application and the ADF4159 which is apparently the same than the ADF4158 but in 13 GHz version will exhibit the same 'problem'.

    Actually if there is no way to drastically improve this behavior I do not see any application where this could be acceptable meaning that this PLL is usable only at frequencies far from the PFD frequency multiples if I understand well. this is quite limiting and not clear from the datasheet reading.

    One thing made me confusing. I had a datasheet downloaded few months ago in revision B which doesn"t mention the NEG BLEED CURRENT setting in R4. It appears apparently in Rev C. The version currently available is Rev D but if you google ADF4158, the second link says Rev C whereas this is actuelly the Rev D which is downloaded. One learnt think, always get the datasheet from the manufacturer's website and not from a google link to the manufacturer's website....

    Now regarding the NEGATIVE BLEED CURRENT setting, I've turned the setting from 0 to 11 and this has increased the close phase noise which was already quite bad (-50dBm), This increased noise is masking a bit the moving carriers but they are still there with same level. The only benefit is that the close phase noise level doesn't change anymore when the 'moving' spurs are coming close to the carrier but it has degraded the overall phase noise apparently.

    I had already added a bias voltage on the inverting loop filter with a bridge resistor on the V+ of the OPAMP. This bias is about 3V (VCO tuning range is 12V).

    On the document you're mentionning I do not understand the table 1 on page 5 which shows some bleed % depending from the CP current. What shall we do with that ? Do I need to tune the bias on the filter according to the CP current ?

    My application is using CP=5mA. But I'm not sure I have as well understood the interrest of adjusting this CP to some other values as long as the loop filter is calculated in accordance.



  • If you want something similar to the ADF4158, without the high-order modulus, you should consider the ADF4153A - it has a 12-bit programmable modulus; a normalized phase noise floor of -223 dBc/Hz.

    Is the 12 GHz LO a fixed frequency application? If so, maybe consider using the Int-N ADF41020. Alternatively, when using the ADF4159, you can use the programmable negative bleed current to remove the moving spur.

    I agree. Always go to for the latest, most up-to-date data sheets.

    On the ADF4157 and ADF4158, when negative bleed is enabled, the negative bleed current is a percentage of programmed charge pump current. Hence, different charge pump currents will have different results on the moving spur. If you experiment with programming different charge pump currents, you will find that there is only an improvement at one or two of the available currents. In your system, it looks like CP = 5 mA is not one of the settings that improves the moving spur. Can you try programming different currents and seeing is there any improvement?

  • Hi,

    Enabling the negative bleed current has improved but not enough. I haven't yet changed the CP as it requires to change the loop filter components also right ? I'll try next week.

    Regarding the noise floor, I'm surprised to see that there is no much difference between interger PLL and fractionnal PLL. You're talking about -223dBc/Hz whereas the ADF4158 exhibit -216 dBc/Hz... However 12-bits might be not enough for what I intend but I will investigate further on the ADF portfolio and probably try some other chips.

    I'll try adjusting CP and will let you know if it improves significantly or not.



  • You can test the various CP currents without changing the loop filter components. It will change the bandwidth and phase margin of the loop filter but it will give you an indication of if the CP current has an effect.

    When you find a 'good' CP current, you could then re-design the loop filter for the new CP current.

    The ADF4153A is a Fractional-N PLL too. If you give me your requirements, I can recommend a part.

  • I've swept all the CP values from 5.00 to 0.31mA : the spurs at 10 and 20 MHz have decreased from 5 to 2.81 mA (only two values were showing no apparent effect). Then at 2.5 mA it came back to the level of 5mA and decreased again down to 0.31mA.

    The two lowest spurs values are at 2.81 and 0.31mA but they do not exhibit the same phase noise. see attached picture. The 0.31 has a higher close phase noise but which decreases faster than the 2.81mA.

    The 'moving' spurs are here at any CP value but their amplitude depend on CP values.

    At that point the best value sounds to be 0.31mA but I would be please to improve the close phase noise

    Few questions :

    1. Will the CP setting have an effect an all frequencies or may it be possible that CP needs do be adjusted according to the desired frequency (which would be rather impossible to achieve) ?

    2. Will the CP value depend on the VCO used ?

    3. In fact, how this CP setting acts on the phase noise and spurs ? Is there a way to predict that or shall it be tested for all values in a design from experimentation before choosing the correct value ?

    Regarding my requirement, I need to have of course the best phase noise and the lowest spurs as possible with the the maximum frequency resolution. From that, everything is compromise but I would like to get a close phase noise better than what I have, without degrading too much the far phase noise and reducing spurs at maximum. Frequency resolution could be decreased but should remain in the range of 1 KHz. The moving spurs are not acceptable.

    If you have any suggestion this would be interresting but get your feedback.

  • Another interresting plot attached.

    I've measured phase noise for all CP parameters.

    On that plot, I've selected the 8 which are the most representative of different behaviors.

    Finally the best compromise could be CP=0.94mA achieveing a good phase noise at 10 KHz but higher broadband noises

  • The fractional-N spur performance is very sensitive to the linearity of the phase detector around zero phase error (very short current pulses). I'm suspicious of the loop filter chosen

    which requires the op-amp to act in a linear fashion when presented with current pulses only a few ns in length.

    Try adding R1 and C1 to change it to

    where R1 and C1 act as a low pass filter with a cutoff at about 3MHz.

    The phase noise plot should be much closer to the ADIsimPLL predictions. As your in-band phase noise is way off, this is possibly reference noise, do you have a clean reference and are you meeting the slew rate requirement on the reference input?

  • Changing the bleed current from OFF to ON decreases close phase boise (100Hz-10kHz) by 15-20dB and for some CP values it removes somes spurs but for some other CP values it adds spurs !

    This is really difficult to understand what strategy to implement and the impact of these settings.

    See attached plot

    for CP = 0.31 and 0.63 mA with Bleed ON and OFF

    At the moment I'm really far from the performances from ADIsimpPLL simulation My best phase noise I could achieve was arround -88dBc/Hz@10kHz whereas ADIsimPLL shows -105 dBc/Hz and no noise above -100 dBc/Hz..... Any clue for that ?

  • It looks like the negative bleed solution may not be robust enough for you.

    You could implement a frequency plan, where, normally you use a PFD frequency of 10 MHz, but then, at problematic output frequencies, you change the PFD frequency to 6.66 MHz. This will move the integer boundary and hence move away from the 'moving' spur region.

    To do this, enable the reference input doubler and set the R-divider to 3.