I am using ADF4351 for WLAN design and my LO phase noise requirement is -95dBc at 100KHz. My REF is 30.72 MHz crystal (Si8208) and has very good phase noise performance. Using adsimpll, the loop filter is designed for 60Khz and 60 degree. My PFD frequency is 30.72MHz. Although I designed for above said loopfilter BW, I see from measurements little similarity between simpll and actual loop filter performance. My main questions are
- how much similar are the values in practice.
- How one has to progress with the optimizing phase noise performance.
It is mentioned in one of the questions regarding the noise performance getting worse with low pll BW. My initial measured phase noise was very bad with -45dBc at 30Hz. Does the LO becomes jittery at low filter BW ?..
It looks ilke the switching regulator is the problem. Please try an LDO, like the ADP150.