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ADF4351 evaluation board - large spurs in signal - what to do?

Hi,

I'm in a process of testing  UG-435 evaluation board for ADF4351 PLL IC.

With any phase detector frequency and any VCO freq. I get a signal with two close side spurs, which are pretty strong (-30 dBc), for example, at 200 kHz CP freq. and division by 4 (1000 MHz RF output, 50 kHz channel spacing) these spurs are +/-2.5 kHz from carrier, i.e. +/- 10 kHz from VCO frequency (4 GHz).

CP current is set to 5 mA, when I write lower values into the device, spurs get worse and if I set CP current lower than 2 mA, then spurs multiply into several of those.

Spurs do not react to any RF out power and phase settings' changes.

My question is - should  evaluation board output signal look like this or I do something wrong?

What might be the nature of these spurs, what would be a way to address this issue?

My band of interest is 960-1030 MHz.

I attach spectrum analyzer screen, for a 1000 MHz signal, 50 kHz span, CP comparison frequency is 200kHz, VCO divided by 4. Spurs are 2.5 kHz apart from signal.

Thanks.

Would appreciate any feedback or advise.

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  • Thanks for your prompt reply.

    I'm trying to build an exciter for radar transmitter, operating in 960.6-1000.5 MHz band, with 700 kHz channel spacing / steps. That is my end task.

    I thought initially of implementing Integer-N design with a VCO running at 400 kHz spacing thus giving 100 kHz after division by 4.

    However if you can advise on how to do this better with fractional divider and higher PFD frequency - this would be extremely helpful. What values should I enter?

    I'm not in a lab now so I can't post screenshot, but I've entered RF Freq. setting - 962 MHz, 50 kHz (200 kHz @VCO), R counter = 125 for onboard 25 MHz TCXO, 5 dBm RF output, tried both low noise and low spur modes.

Reply
  • Thanks for your prompt reply.

    I'm trying to build an exciter for radar transmitter, operating in 960.6-1000.5 MHz band, with 700 kHz channel spacing / steps. That is my end task.

    I thought initially of implementing Integer-N design with a VCO running at 400 kHz spacing thus giving 100 kHz after division by 4.

    However if you can advise on how to do this better with fractional divider and higher PFD frequency - this would be extremely helpful. What values should I enter?

    I'm not in a lab now so I can't post screenshot, but I've entered RF Freq. setting - 962 MHz, 50 kHz (200 kHz @VCO), R counter = 125 for onboard 25 MHz TCXO, 5 dBm RF output, tried both low noise and low spur modes.

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