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ADF4156 Design Issue at 1911.642 MHz

Hello!

I've been using ADF4156 to design Local Oscillators at frequencies in the range of 5 to 6 GHz.

I use ADISimPLL and Fraction N software for the design.

I haven't faced any difficulties in the LO design at the above mentioned frequencies; but, i am facing difficulties in designing a LO at 1911.642 MHz.

The LO worked fine initially, but, strangely enough, it stopped working afterwards.

The charge pump output voltage is at 0.4V to 0.5V no matter what register configuration i use.

Further, the PLL chip gives out 5V at the charge pump out if i only enable the charge pump supply.

I've also designed a test PCB of ADF4156, but the PLL chip responds the same way.

Kindly help me in resolving this issue.

Am i programming the chip wrong?

It should not be the case as the LO was working initially.

An example for designing the LO at 1911.642MHz using Fraction N software and ADISimPLL would be highly helpful.

Thanking you in anticipation.

With best regards,

Humayun Zahid

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  • Hello Humayun,

    When using a Fractional N PLL, your design should aim to use the highest PFD frequency possible in order to get optimum filtering of the sigma delta noise ...see attached a .pll file to generate 1911.642Mhz ( usign a PFD = 5MHz), you can see this using the ADIsimPLL by reducing the PFD frequency to 1MHz ( maintain default values for the loop filter) ...you will see the sigma delta noise increase significantly...

    Using the lowest prescaler value , allows you to use the highest PFD possible for your design...and so push out the sigma delta noise.

    I hope this helps.

    Brigid.

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  • Hello Humayun,

    When using a Fractional N PLL, your design should aim to use the highest PFD frequency possible in order to get optimum filtering of the sigma delta noise ...see attached a .pll file to generate 1911.642Mhz ( usign a PFD = 5MHz), you can see this using the ADIsimPLL by reducing the PFD frequency to 1MHz ( maintain default values for the loop filter) ...you will see the sigma delta noise increase significantly...

    Using the lowest prescaler value , allows you to use the highest PFD possible for your design...and so push out the sigma delta noise.

    I hope this helps.

    Brigid.

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