Post Go back to editing

ADF4156 Design Issue at 1911.642 MHz

Hello!

I've been using ADF4156 to design Local Oscillators at frequencies in the range of 5 to 6 GHz.

I use ADISimPLL and Fraction N software for the design.

I haven't faced any difficulties in the LO design at the above mentioned frequencies; but, i am facing difficulties in designing a LO at 1911.642 MHz.

The LO worked fine initially, but, strangely enough, it stopped working afterwards.

The charge pump output voltage is at 0.4V to 0.5V no matter what register configuration i use.

Further, the PLL chip gives out 5V at the charge pump out if i only enable the charge pump supply.

I've also designed a test PCB of ADF4156, but the PLL chip responds the same way.

Kindly help me in resolving this issue.

Am i programming the chip wrong?

It should not be the case as the LO was working initially.

An example for designing the LO at 1911.642MHz using Fraction N software and ADISimPLL would be highly helpful.

Thanking you in anticipation.

With best regards,

Humayun Zahid

Parents
  • Hello Humayun,

    Our recommendation for best phase noise performance is to always use the lowest prescaler allowable , in addition  so that you have the widest N ( integer value available), for P = 4/5, N = 23, P = 8/9, N = 75. ...a min value for N called the minimum continuous divide ratio so that N will not be an illegal value.

    Can you confirm that you were not using an "illegal " N value.

    Regards,

    Brigid.

Reply
  • Hello Humayun,

    Our recommendation for best phase noise performance is to always use the lowest prescaler allowable , in addition  so that you have the widest N ( integer value available), for P = 4/5, N = 23, P = 8/9, N = 75. ...a min value for N called the minimum continuous divide ratio so that N will not be an illegal value.

    Can you confirm that you were not using an "illegal " N value.

    Regards,

    Brigid.

Children
No Data