Single Sided Configuration - AD8362

Hi,

I am trying to measure the RMS value of 20MHz to 100MHz sinusoid generated from AD9951 DDS using AD8362 using single ended configuration as shown in the PIC attached.

When I feed amplitude of 3.0VP-P, I find the RMS value output VOUT measured through a DMM to be much lower than expected i.e Equation '9' VOUT = VSLP log10[rms(VIN)/VZ] or for that matter the curve shown in Figure 49. I have checked that maximum input in this range can be 2.23Vrms, still I am finding the RMS output to be lower in my case.

There after when I reduce the 1.5Vp-p or of that order, I still find the VOUT is 250mV lower than expected output for 20MHZ. This error again is not same for all frequencies and varies from 250mV to 450mV or so. I am really very confused. I do not know what to do get extremely good accuracy and better dynamic range.

We use Cin = 20nF, 20nF. DECL = 1nF, CHPF = 1nF and CLPF = 330pF.

Kindly show some light in this regards.

Parents
  • Is the output of the AD9951 buffered? This is a current out DAC whose voltage is formed by the load resistance. If the AD8362 circuit is connected directly to the AD9951 then the DAC will see a lower load which will give lower voltage.

    One way of checking this is to probe the voltage at the AD8362. Check the voltage on R33 and also on pins 4 and 5  of AD8362.

    Based on Figure 49, 3 V pp (13.5 dBm re:50 ohms) is much too high of a level to be driving into this circuit.

Reply
  • Is the output of the AD9951 buffered? This is a current out DAC whose voltage is formed by the load resistance. If the AD8362 circuit is connected directly to the AD9951 then the DAC will see a lower load which will give lower voltage.

    One way of checking this is to probe the voltage at the AD8362. Check the voltage on R33 and also on pins 4 and 5  of AD8362.

    Based on Figure 49, 3 V pp (13.5 dBm re:50 ohms) is much too high of a level to be driving into this circuit.

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