ADF4156

The frequency switching time of the ADF4156 will be gated by

1) the write time required to change the o/p frequency, refer to page 4..table 2 for the min timing pulses

2) the lock time of the PLL ..this will be dependant on the loop filter design...a wider loop filter will give faster settling time , but can be at the expense of increase spur levels and phase noise and ...using ADIsimPLL can determine lock time /phase noise/ spur levels

regards,

Brigid.

Brigid thank you for your help I set up ADIsimPLL and result is in below. I didnt figured out what is maximum hoping number(hops/second) in light of the figures of ADIsimPLL.

Thanks

Ahmet

You can see how long it will take to jump from one frequency to another in the TimeDomain window. You can set the frequency jump in the TimeDomain control on the bottom left of the software.

For example, in your screenshot above, it takes 175 µs to jump from 915 MHz to 930 MHz. You can reduce this time by increasing the loop filter bandwidth.

For a full introduction to ADIsimPLL, watch this video: http://videos.analog.com/video/products/rf-ics/756428873001/ADIsimPLL-Development-Software/