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HMC679 Last Time Buy
The HMC679LC3C is a T Flip-Flop w/Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted...
Datasheet
HMC679 on Analog.com

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HMC679 reset pin



		

			

									
					    pelican2
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jan 28, 2015 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Creating a design with the HMC679 F/F and want to use the reset input to control ( inhibit / enable ) the toggling.
    
 
    This will be a DC control signal, but there is no info about required input signal levels / voltages / currents / recommended circuits to do this. The EVAL board schematic shows nothing, also.
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 Logic Devices
                
                                                    
                 Flip-Flop Electronics
                
                                                    
                 HMC679
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jan 29, 2015 8:46 PM
            
            
					
      
	
      

		
		
      
					
      hi pelican2,
      
 
      The datasheet specifies that the HMC679LC3C are Current Mode Logic (CML) logic levels but I guess it needs to be more clear and improved.  I have attached the application note which describe in details this versatile I/O interface in section 3.  Figure 3.2,3.3 give you the min.max levels of the CML Input.  For full speed of 26GHz,the I/O should be interfaced with widely used advance 1.2V CML FPGA's. Section 4 of the document gives all possible interface circuits to different I/O standards.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Aug 2, 2018 10:54 AM
            
            
					
      
	
      

		
		
      
					
      This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

      Thank you,
      EZ Admin
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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