ADIsimFrequencyPlanner enables fast, accurate simulation and elimination of integer boundary spurs from Analog Devices PLL synthesizers. The tool analyzes the user's output requirements, and then optimizes the PFD frequency for each output step to give the best integer boundary spur performance. The optimum PFD frequency is selected by changing the output divider of the clock generation chip (e.g. HMC7044) and changing the reference input divider of the PLLVCO (e.g. ADF5355, HMC830).

Typical results are better than -100 dBc for integer boundary spurs across output frequencies from 55 MHz to 13.6 GHz.

Attached files:

  • ADIsimFrequencyPlanner_HMC7044_ADF5355_HMC704_vX.pdf - start here - description of the application and the ADIsimFrequencyPlanner software.
  • - Windows installation files.
  • ADIsimFrequencyPlanner_Tutorial_vX.pdf - Tutorial for using the ADIsimFrequencyPlanner software.

Change history:

  • v2.1.1: Bug fix to ADF4351 model.
  • v2.1.0: Added option to select either HMC830 or ADF4351 as reference source PLL in cascaded mode.
  • v2.0.2: Added cascaded PLLVCO feature. Now a second PLLVCO in integer-N mode can be used as the reference source.
  • v1.0.0: Initial release.