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HMCAD5831 Obsolete
The HMCAD5831LP9BE is a wideband 3-bit analog-to-digital converter with over/under range bit. The converter operates at typical speeds of up to 26 GSPS...
Datasheet
HMCAD5831 on Analog.com

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HMCAD5831  time delay

		
	
				

			

									
					    masafumi
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on May 13, 2015 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hallow! I'm the beginner of this community. 
    
 
    I’m interested in  HMCAD5831, but there are some questions for the operation.
    
 
    There is no information for time delay in any specification sheet.
    
 
    Please inform us the time delay from input to output @ 25GHz CLK.
    
 
    I hope it within 80ps.
    
 

    
 
    Regards,
    
 

    
 
    Masafumi
    
			
    
			
									
		                             
                        

    
    
                                            
                 hmcad5831
                
                                                    
                 High Speed A/D Converters >10 MSPS
                
                                                    
                 Standard High Speed A/D Converters
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                                                    
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on May 13, 2015 3:28 PM
            
            
						
			            		
      
		
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      Please refer to the timing diagram shown on page 4 of the datasheet. At the bottom of this page, Note 2 states that the latency through the device is 1.5 sampling clock cycles plus a small amount of sub-cycle delay. So the delay through the device in seconds depends upon your clock rate. At a sample rate of 20GS/s, which is 50psec cycle time, the delay would be greater than 75psec and no more than 125 psec.
      
 
      Thanks.
      
 
      Robbie
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
				
				
				
		
		
      
			
		
      
	
      

      

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                on Aug 2, 2018 11:02 AM
            
            
						
			            		
        
		
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        This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

        Thank you,
        EZ Admin
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
				
						
				
				
				
		
		
        
			
		
        
	
        

        

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