Hi!
Greetings!
I have following doubts in the context of AD8302:
1. I have coupler designed at 50ohm terminating impedances at my operating frequency (150MHz). I also know that if coupler sees an impedance which is different from 50ohm, the RF characteristics will be ruined (coupling, directivity,...)
In between coupler and AD8302, there is an attenuator (to ensure the power remains in the input limits of AD8302).
Hence, I want to ensure that no impedance mismatch occurs in between coupler and attenuator, as well as, in between attenuator and AD8302.
AD8302 chip inputs (INPA and INPB) have R and C are connected. If I select their values as suggested in the datasheet reflectometer application (R1 = R2 = 52.3 Ω, C1=C4=C5=C6=1nF), would it be fine? In this case what would be the input impedance at 150 MHz? So I can match create a matching between attenuator and the chip? (Or is it really required to match this? However, I can see that coupler response highly degrades once it doesn't see 50ohm at it's output). I would be prefer to have direct connection from MSET to VMAG and PSET to VPHS.
2. For the values mentioned (R1 = R2 = 52.3 Ω, C1=C4=C5=C6=1nF), what would be the corner frequency?
As somewhere in datasheet, it is mentioned that the corner frequency should be less than the operating frequency (if I am wrong, please correct me).
COPIED paragraph from datasheet (just to clarify in which context I am raising my query):
{
There is an internal 10 pF capacitor to ground
that sets the maximum corner to approximately 200 MHz.
The corner can be lowered according the formula fHP (MHz) =
2/CC(nF), where CC is the total capacitance from OFSA or OFSB
to ground, including the internal 10 pF.
AND ALSO
The signal path is fully differential
to minimize the effect of common-mode signals and noise.
Since there is a total of 60 dB of cascaded gain, slight dc offsets
can cause limiting of the latter stages, which may cause measurement
errors for small signals. This is corrected by a feedback
loop. The nominal high-pass corner frequency, fHP, of this loop
is set internally at 200 MHz but can be lowered by adding external
capacitance to the OFSA and OFSB pins. Signals at frequencies
well below the high-pass corner are indistinguishable from dc
offsets and are also nulled.
}
My question is what should be the selection of R and C values to meet the requirements?
3. I would be happy if I can get SPICE nonlinear model/ Agilent ADS model, S-parameter file. It would allow us to minimize the fabrication cycles.
