HMC365 outputs levels are PECL compatible ?

Hello, I am working about a prescaler using an HMC365S8G followed by an ECL divider by 4 as high side of enclosed pdf schematic.

The questions are:

1)  If I use a differential output termination for the HMC365 the common mode DC voltage is the same for both output, then may I      eliminated the outputs capacitors ?

2)  From the HMC365 datasheet ( page 3 ) I see ' VLogic  Vcc-1.6V to Vcc-1.2V' , if this is the DC output level of the device it seem to be

     compatible with the input bias level of the ECL prescaler ( about Vcc-1.3V to Vcc- 1.4V), so may I eliminated the input bias circuits and

     directly connect to HMC365 outputs ?

The device output power (4-6 dBm corresponding to 1.00 -1.26 Vpp) is ok for the ECL divider inputs.

If these modifications are possible the schematic turn out as the bottom side of the enclosed pdf, more simple and more RF advantageous

(without the bias and DC blocking capacitor the 100Ohm termination can be put close to the ECL divider inputs).

I ask all this because prototyping at these frequencies is expensive both in time and money ( an 'ad hoc' pcb is need for each solution, not easy breadboard allowed !).

In advance thanks for any comments, best regards

Baciccia

Prescaler.pdf
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  • 0
    •  Analog Employees 
    on Jul 14, 2015 12:47 AM over 5 years ago

    Hi there,

    Regarding the logic levels, the HMC dividers are CML'ish. We recommend against DC coupling the HMC dividers as the logic levels aren't DC compatible with one another. The outputs of the HMC365S8G are 50 ohms so not sure why the upper schematic includes shunt 50 ohm matching resistors prior to the 1nF cap and unfortunately I'm not familiar with Micrel dividers or their input impedances to provide much help on the input to the SY100EL33. From looking at your schematic it looks like you need a total divide ratio of 16. Depending on your input frequency, you could use a 2nd HMC365S8G to retain the 25% duty cycle or if duty cycle isn't a concern perhaps the programmable HMC705LP4E could be used for a single solution (or cascade). These are easily AC coupled and offer low residual phase noise performance. A link to an FAQ for HMC Microwave Frequency Dividers is attached as well as the datasheet for the HMC705LP4E is attached.

    FAQ: HMC Microwave Frequency Dividers by Analog Devices

    Best Regards,

    Marty

    ADI_hmc705lp4.pdf
Reply
  • 0
    •  Analog Employees 
    on Jul 14, 2015 12:47 AM over 5 years ago

    Hi there,

    Regarding the logic levels, the HMC dividers are CML'ish. We recommend against DC coupling the HMC dividers as the logic levels aren't DC compatible with one another. The outputs of the HMC365S8G are 50 ohms so not sure why the upper schematic includes shunt 50 ohm matching resistors prior to the 1nF cap and unfortunately I'm not familiar with Micrel dividers or their input impedances to provide much help on the input to the SY100EL33. From looking at your schematic it looks like you need a total divide ratio of 16. Depending on your input frequency, you could use a 2nd HMC365S8G to retain the 25% duty cycle or if duty cycle isn't a concern perhaps the programmable HMC705LP4E could be used for a single solution (or cascade). These are easily AC coupled and offer low residual phase noise performance. A link to an FAQ for HMC Microwave Frequency Dividers is attached as well as the datasheet for the HMC705LP4E is attached.

    FAQ: HMC Microwave Frequency Dividers by Analog Devices

    Best Regards,

    Marty

    ADI_hmc705lp4.pdf
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