ADF4351 PLL Lock problem

It looks like your loop filter is unstable. How did you design it? If you used ADIsimPLL, please post the .pll file. What charge pump current did you design the filter for? Make sure the ADF4351 is programmed for the same charge pump current.

Thanks for your reply.

I attached the ADISimPLL file.

I designed a filter to have a good phase noise. The phase margin is more than 45 °.

The charge pump current is 5 mA. I programmed this value in registers.

The loop filter looks good. Can you share your register settings and schematic?

Is there any possibility your reference frequency is sweeping?

What happens when you program the charge pump current to the minimum value? Does it have any effect on the output spectrum?

By the way, the ADF4351 cheat sheet may help you: https://ez.analog.com/message/156447

I attached the schematic.

R0 = 0x780000;

R1 = 0x8011;

R2 = 0x18004142;

R3 = 0x4004B3;

R4 = 0xB5003C;

R5 = 0x580005;

The frequency reference can't sweep.

If I programmed the charge pump current to the minimum value, the output spectrum sweeps less than 5 mA.

There may be a problem with your SPI writing. It looks like there might be an extra, unwanted SCK pulse.

Try these:

• Set SCK low after the last clock cycle.
• Leave LE high until the start of the next register write.

Your register settings look good, however, as an experiment, set:

• ABP (R3[22]) to 0.
• LDF (R2[8]) to 0.

I upgraded my software to improve the SPI communication.

I tested with :

• ABP (R3[22]) to 0.
• LDF (R2[8]) to 0.

I have no change.

At 300 MHz, the PLL is locked at the beginning but it is unlocked a few time after.

I tested at 310 MHz, I don't understand why the PLL doesn't lock.

So, initially, after writing the registers, the output is locked and stable? How long does it take for it to go unstable? Is there anything happening on the SPI interface just before it goes unstable?

When I set up the PLL at 300 MHz in integral mode, it works well.

R0 = 0x780000;

R1 = 0x8011;

R2 = 0x5F42;

R3 = 0x4004B3;

R4 = 0xB5003C;

R5 = 0x580005;

But in fractionnal mode at the same frequency, it doesn't lock. I have a 450 MHz signal at the output.

If I change the frequency in integral mode to 310 Mhz, for example, I have the right frequency but it is unstable.

"in fractionnal mode at the same frequency" - how are you in fractional-N mode if you are at 300 MHz output? Please share your settings for fractional mode.

Try toggling the prescaler (R1[27]) and/or the divided/fundamental feedback (R4[23]). See if either makes a difference.

I changed LDF & ABP values, I have a 342 MHz signal at the output.

R0 = 0x780000;

R1 = 0x8011;

R2 = 0x5E42;

R3 = 0x4B3;

R4 = 0xB5003C;

R5 = 0x580005;

With fundamental feedback, I have a 300 MHz signal (INT-N mode) but the phase noise is bad near the carrier.

I used an oscillator with a good phase noise.

With divided feedback, it is unstable.

I have just changed the die and it is worst than before. The PLL is unstable at 300 MHz.