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What is the minimum Cn value on ADF4360-2

The ADF4360-2 integrated PLL/VCO has a decoupling node (Cn, on pin 14) which is decoupled with a large value capacitor.

In the datasheet this is variously described as a 10uF (for best phase noise) and 440nF (a compromise between phase noise and turn-on time).
   What is the actual MINIMUM value for this part ?

   Can I reduce it ad-infinitum (resulting in ever more degraded VCO phase noise) or is there a value below which the bias system in the VCO core goes unstable.

   I need an "offical" answer if possible, as running a part outside it's data sheet definitions does not make for good sleep.

  • Hello Michael,

    The time interval required between the control latch and N latch depends on the value of the Cn capacitor,  as the settling time on the CN pin is determined by a 1mA charging current from the bias generator.

    This current will vary from run to run depending on the sheet resistance of the Fab lot, It would be wise to allow a 10 to 20% margin on the time interval between the control and N counter write in order to guarantee
    that the part locks reliably.



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