The ADF4360-2 integrated PLL/VCO has a decoupling node (Cn, on pin 14) which is decoupled with a large value capacitor.
In the datasheet this is variously described as a 10uF (for best phase noise) and 440nF (a compromise between phase noise and turn-on time).
What is the actual MINIMUM value for this part ?
Can I reduce it ad-infinitum (resulting in ever more degraded VCO phase noise) or is there a value below which the bias system in the VCO core goes unstable.
I need an "offical" answer if possible, as running a part outside it's data sheet definitions does not make for good sleep.
