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Why am I unable to repeat the phase alignment between RFin and REFin using the ADF4106?

I an using "Analog Devices Int-N PLL Software" with the USB interface to control an ADF4106.  Is it possible to achieve the same phase relationship between the RFin and REFin signals for a given set of device settings after power-cycling the ADF4106 and VCO?

I have tried the "Initialization Latch Method" and the "Counter Reset Method" as described in the ADF4106 data sheet.  It seems that for frequency settings where RFin is not a multiple of REFin the resulting phase relationship is always different after power-up.  I was expecting that the internal reset pulse or the counter reset operation would ensure that a consistent phase relationship would result.  It does not.  In fact, any counter reset that is executed results in a different phase relationship for the cases where RFin is not a multiple of REFin.  Am I missing something?

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  • I got the REFin and RFin to synchronize for all settings! I have been using the 10MHz reference signal from the back of a bench top signal generator as my measurement system's phase reference.  The same signal generator makes the 100MHz REFin signal.  If I use this system 10MHz reference at the flip flop instead of the 100MHz REFin signal, then I get the consistent phase results that I desire. I believe that it is because this configuration synchronizes the R counter output (and the PLL) with the measurement system's 10MHz reference.  In other words, now the PLL chip only counts the 10 cycles that happen following the system 10MHz reference pulse.  Previously, it could count 10 cycles with the system pulse happening at any one of the10 different spots in the count.  This accounts for the phase differences that I observed.

    Thank you for your assistance and please let me know if my observations or conclusions seem flawed.

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  • I got the REFin and RFin to synchronize for all settings! I have been using the 10MHz reference signal from the back of a bench top signal generator as my measurement system's phase reference.  The same signal generator makes the 100MHz REFin signal.  If I use this system 10MHz reference at the flip flop instead of the 100MHz REFin signal, then I get the consistent phase results that I desire. I believe that it is because this configuration synchronizes the R counter output (and the PLL) with the measurement system's 10MHz reference.  In other words, now the PLL chip only counts the 10 cycles that happen following the system 10MHz reference pulse.  Previously, it could count 10 cycles with the system pulse happening at any one of the10 different spots in the count.  This accounts for the phase differences that I observed.

    Thank you for your assistance and please let me know if my observations or conclusions seem flawed.

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