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Why am I unable to repeat the phase alignment between RFin and REFin using the ADF4106?

I an using "Analog Devices Int-N PLL Software" with the USB interface to control an ADF4106.  Is it possible to achieve the same phase relationship between the RFin and REFin signals for a given set of device settings after power-cycling the ADF4106 and VCO?

I have tried the "Initialization Latch Method" and the "Counter Reset Method" as described in the ADF4106 data sheet.  It seems that for frequency settings where RFin is not a multiple of REFin the resulting phase relationship is always different after power-up.  I was expecting that the internal reset pulse or the counter reset operation would ensure that a consistent phase relationship would result.  It does not.  In fact, any counter reset that is executed results in a different phase relationship for the cases where RFin is not a multiple of REFin.  Am I missing something?

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  • If the second suggestion is used, then won't the LE signal be unable to "get through" the flip flop when in the counter reset mode since the R counter is suspended?  It will not be possible write to any of the latches if this happens.

    The suggestion to set the mux output to look at the R counter is a good one.  I have been looking at the phase relationships between the R counter output and the REFin signal before and after executing counter resets.  I have done cases when RFin is in multiples of 100MHz and when it is not.  I am not measuring any change in the relative phases, viewing on an oscilloscope.  This should be expected since the flip-flop is still in the circuit connected to the REFin and LE.

    The RFin to REFin phase is still changing as previously described.  There must be another reason for this change. Can you think of any other possible causes?  (Thank you for your prompt responses BWT.)

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  • If the second suggestion is used, then won't the LE signal be unable to "get through" the flip flop when in the counter reset mode since the R counter is suspended?  It will not be possible write to any of the latches if this happens.

    The suggestion to set the mux output to look at the R counter is a good one.  I have been looking at the phase relationships between the R counter output and the REFin signal before and after executing counter resets.  I have done cases when RFin is in multiples of 100MHz and when it is not.  I am not measuring any change in the relative phases, viewing on an oscilloscope.  This should be expected since the flip-flop is still in the circuit connected to the REFin and LE.

    The RFin to REFin phase is still changing as previously described.  There must be another reason for this change. Can you think of any other possible causes?  (Thank you for your prompt responses BWT.)

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