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ADF4106 Production
The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and...
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ADF4106 on Analog.com

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Why am I unable to repeat the phase alignment between RFin and REFin using the ADF4106?

    
		

			

									
					    Alroy
					
							


			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jan 13, 2016 
				
			
			
		
    
		
     
				
		
    
		    		    
		    
		    	
			
    I an using "Analog Devices Int-N PLL Software" with the USB interface to control an ADF4106.  Is it possible to achieve the same phase relationship between the RFin and REFin signals for a given set of device settings after power-cycling the ADF4106 and VCO?
    
 
    I have tried the "Initialization Latch Method" and the "Counter Reset Method" as described in the ADF4106 data sheet.  It seems that for frequency settings where RFin is not a multiple of REFin the resulting phase relationship is always different after power-up.  I was expecting that the internal reset pulse or the counter reset operation would ensure that a consistent phase relationship would result.  It does not.  In fact, any counter reset that is executed results in a different phase relationship for the cases where RFin is not a multiple of REFin.  Am I missing something?
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 Integer-N PLL
                
                                                    
                 adf4106
                
                                                    
                 Phase Locked Loop (PLL) Synthesizer & Translation Loop
                
                                                    
                 rf and microwave
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jan 22, 2016 3:17 PM
            

            
					
      
	
      

		
		
      
					
      You R divider value = 10. So, every 10th reference cycle, you are getting a pulse from the R divider output. If you release counter reset at different times relative to this R divider output pulse, you'll get a different phase relationship. If you could consistently release counter reset at the same time, relative to the R divider output, I think you'll get a consistent phase.
      
 
      Could you try one of these:
      
 
        
  
      • Feed your reference signal into your DSP/microcontroller/FPGA and count the number of reference cycles. The release counter reset at the same time every time. 
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      • Set Muxout to R divider output. Feed the muxout output to your flip-flop (instead of the reference signal) and use this to ensure the register writes are always synchronized with the R divider output.
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													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jan 22, 2016 3:17 PM
            

            
					
      
	
      

		
		
      
					
      You R divider value = 10. So, every 10th reference cycle, you are getting a pulse from the R divider output. If you release counter reset at different times relative to this R divider output pulse, you'll get a different phase relationship. If you could consistently release counter reset at the same time, relative to the R divider output, I think you'll get a consistent phase.
      
 
      Could you try one of these:
      
 
        
  
      • Feed your reference signal into your DSP/microcontroller/FPGA and count the number of reference cycles. The release counter reset at the same time every time. 
        • 
  
      • Set Muxout to R divider output. Feed the muxout output to your flip-flop (instead of the reference signal) and use this to ensure the register writes are always synchronized with the R divider output.
        • 
 
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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