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Why am I unable to repeat the phase alignment between RFin and REFin using the ADF4106?

I an using "Analog Devices Int-N PLL Software" with the USB interface to control an ADF4106.  Is it possible to achieve the same phase relationship between the RFin and REFin signals for a given set of device settings after power-cycling the ADF4106 and VCO?

I have tried the "Initialization Latch Method" and the "Counter Reset Method" as described in the ADF4106 data sheet.  It seems that for frequency settings where RFin is not a multiple of REFin the resulting phase relationship is always different after power-up.  I was expecting that the internal reset pulse or the counter reset operation would ensure that a consistent phase relationship would result.  It does not.  In fact, any counter reset that is executed results in a different phase relationship for the cases where RFin is not a multiple of REFin.  Am I missing something?

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  • For REFin=100MHz, Fpfd=10MHz, and RFin=3000MHz, when I do "Write Initialization Latch" followed by "Write N Counter Latch" then the same phase relationship will always result for all trials.  If RFin is changed to RFin=3010MHz, then a different phase relationship will result for each trial of "Write Initialization Latch" followed by "Write N Counter Latch".

    Here are a few more observations that might be helpful.  For all RFin settings that are multiples of 100MHz, the resulting phase is consistent for that frequency setting.  For RFin settings that are multiples of 50MHz, there seem to be only two discrete phase states that result for each setting.  These behaviors were also observed before the flip-flop was added to the circuit.

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  • For REFin=100MHz, Fpfd=10MHz, and RFin=3000MHz, when I do "Write Initialization Latch" followed by "Write N Counter Latch" then the same phase relationship will always result for all trials.  If RFin is changed to RFin=3010MHz, then a different phase relationship will result for each trial of "Write Initialization Latch" followed by "Write N Counter Latch".

    Here are a few more observations that might be helpful.  For all RFin settings that are multiples of 100MHz, the resulting phase is consistent for that frequency setting.  For RFin settings that are multiples of 50MHz, there seem to be only two discrete phase states that result for each setting.  These behaviors were also observed before the flip-flop was added to the circuit.

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