Why am I unable to repeat the phase alignment between RFin and REFin using the ADF4106?

The issue is that you're disabled counter reset at different times relative to the reference signal. To do what you want, the register write that disables counter reset must be synchronized with the reference signal; specifically, the rising-edge of LE on the register write must be synchronized with the reference signal.

This isn't possible on the evaluation board. Two solutions:

1. Put your LE signal and reference signal through a flip-flop to synchronize the two.
2. Run your reference signal through your microcontroller/FPGA/DSP (the same one that's writing the SPI signals) and synchronize them that way.

I have added a D-type flip-flop to the PLL circuit to synchronize the LE to the REF signal.  I have confirmed that the LE is synchronized to the REF signal using an oscilloscope.  I have also confirmed that the PLL cannot be programmed when the REF signal is removed.  I am still measuring different phase relationships between the RFin and REFin after the counters are reset with all other settings unchanged.  The circuit behavior has not changed in this regard.  Please note that consistent phase relationships do result if the RFin setting is an integer multiple of the REFin frequency.  This was also true before the flip-flop was added.

What are the other possible causes of the phase relationship inconsistencies?

"Please note that consistent phase relationships do result if the RFin setting is an integer multiple of the REFin frequency." Can you give me example settings of this situation (reference frequency, PFD frequency, RF output frequency)? Also, give me an example of the settings where it fails.

For REFin=100MHz, Fpfd=10MHz, and RFin=3000MHz, when I do "Write Initialization Latch" followed by "Write N Counter Latch" then the same phase relationship will always result for all trials.  If RFin is changed to RFin=3010MHz, then a different phase relationship will result for each trial of "Write Initialization Latch" followed by "Write N Counter Latch".

Here are a few more observations that might be helpful.  For all RFin settings that are multiples of 100MHz, the resulting phase is consistent for that frequency setting.  For RFin settings that are multiples of 50MHz, there seem to be only two discrete phase states that result for each setting.  These behaviors were also observed before the flip-flop was added to the circuit.

Can you try the Counter Reset method as described on page 18 of the datasheet?

I have tried using the counter reset operation.  The same behavior is observed.  When the function latch is rewritten with the counter reset disabled, a different phase state results (for cases where the RFin settings are not multiples of REFin).

You R divider value = 10. So, every 10th reference cycle, you are getting a pulse from the R divider output. If you release counter reset at different times relative to this R divider output pulse, you'll get a different phase relationship. If you could consistently release counter reset at the same time, relative to the R divider output, I think you'll get a consistent phase.

Could you try one of these:

• Feed your reference signal into your DSP/microcontroller/FPGA and count the number of reference cycles. The release counter reset at the same time every time.
• Set Muxout to R divider output. Feed the muxout output to your flip-flop (instead of the reference signal) and use this to ensure the register writes are always synchronized with the R divider output.

If the second suggestion is used, then won't the LE signal be unable to "get through" the flip flop when in the counter reset mode since the R counter is suspended?  It will not be possible write to any of the latches if this happens.

The suggestion to set the mux output to look at the R counter is a good one.  I have been looking at the phase relationships between the R counter output and the REFin signal before and after executing counter resets.  I have done cases when RFin is in multiples of 100MHz and when it is not.  I am not measuring any change in the relative phases, viewing on an oscilloscope.  This should be expected since the flip-flop is still in the circuit connected to the REFin and LE.

The RFin to REFin phase is still changing as previously described.  There must be another reason for this change. Can you think of any other possible causes?  (Thank you for your prompt responses BWT.)

I got the REFin and RFin to synchronize for all settings! I have been using the 10MHz reference signal from the back of a bench top signal generator as my measurement system's phase reference.  The same signal generator makes the 100MHz REFin signal.  If I use this system 10MHz reference at the flip flop instead of the 100MHz REFin signal, then I get the consistent phase results that I desire. I believe that it is because this configuration synchronizes the R counter output (and the PLL) with the measurement system's 10MHz reference.  In other words, now the PLL chip only counts the 10 cycles that happen following the system 10MHz reference pulse.  Previously, it could count 10 cycles with the system pulse happening at any one of the10 different spots in the count.  This accounts for the phase differences that I observed.

Thank you for your assistance and please let me know if my observations or conclusions seem flawed.

Excellent, makes sense.