ADF41020 Setting using ADI Int-N PLL S/W

Hello, I am trying to set ADF41020 PLL chip at 17.08032GH using ADI Int-N PLL S/W.

I read the ADF41020EB1Z Evaluation Board user guide note,

1. It said charg pump setting 1 & 2 are 2.5mA, but PLL chip data sheet said Icp max=5.0mA using Rset=5.1K ohm.

Which one I should follow?

2.regarding to the phase detector polality, do I need to set it as Negative?

whereas Most of PLL chips are using Positive.

3. Actually, I am debuging my PLL circuit now, I think the output frequency is trying to lock.

But at that frequency, it is not quite lock to set frequency. I mean the output is slightly moving frequency, I tried to make the higher loop gain, as well as the lower loop band width, but it doen't work. I started the loop R, C values in my design from EV board recommanded values. Then, What are the next suggestions to work out this problem.

4. for debugging I am using the muxout, also. I would like to know the difference between digital  and alalog lock detect signal.

Pls, Help me, Thank you everyone.

  • 0
    •  Analog Employees 
    on Jan 18, 2016 4:01 PM


    1 ) Assuming you have used similar loop filter components, VCO( same Kv as the eval board) and PFD frequency ( channel spacing), and N values, then you should also use the same charge pump current setting.

    note: the loop filter design components can be easily designed using our download software from our web site, you can simulate your design and look at the performance in terms of phase noise and loop stability.

    Using a charge pump setting of 2.5milliamps allows you to widen your loop bandwidth by increasing the charge pump current.

    2)The phase detector polarity is set to positive unless you are using an active filter (using an op-amp in inverting mode)

    3) Use ADI simPLL to model your design ( ensure that you model the Kvco of your VCO, the range of N values, the charge pump current setting and loop filter components)

    4) Digital lock detect provides a CMOS logic high / low to indicate lock/unlock , wheras the Analog lock detect is an open drain o/p, where you need to add a pull up resistor and filter components to indicate a lock/unlock condition, ADIsimPLL can design these values for you.

    The following note explains the operation of both ;

    I have attached a very usefull debug article to help in your PLL debug.

    I hope this helps,



  • Hello,

    Thank you for your answer. it helps me a lot.

    I have additional questions as below.

    1. So, I can use 5.0mA charge pump setting to wide my loop filter, it helps me to implement easy loop filter compare to 2.5mA setting. Am I correct?

    2. Now, I am using Active type loop filter to increase tune voltage up to 12V.

    4. For digital lock detect setting, it seems to me, it doesn't work well, every time I powered up the digital lock goes high eventhough the output frequency is slightly moving. So, I would like to know the digital lock detect works quite well under the condition slightly moving frequency.

    3. Yes, I am using ADIsimPLL s/w. belows are my inputs for loop fiilter design. otherwise are default values.


    Single Output Frequency

    17.08032GHz, PDF=2.56MHz, Ref Freq=61.44MHz

    Charge Pump Vp=3.0, Lock detect = digital filter

    Library Op Amp=Op27, Supply rails 0~+12V

    Custom VCO Kv=0.75MHz/V

    Loop Bandwidth=256KHz, Phase=45 deg.

    With these valus, I have attached schematic, but some values such as C2(617fF), C3(21.6fF) are not possible to use.

    then, What should I do next? Pls, advice me.

    Thank you.

    Regards, YS Park

    p.s. I would like to know the meaning of Charge Pump Gain : 0/1, also.

  • 0
    •  Analog Employees 
    on Jan 19, 2016 10:04 PM


    After you run the ADIsimPLL to build your schematic, you click on tools , there is an option "build", when you click this option, the software selects standard values.

    Can you send me the open loop phase noise plot of your VCO, the optimum loop bandwidth should be chosen such that the open loop VCO noise intersects the closed loop PLL noise.

    NOTE: I generally set the bias and offset currents of the OP-AMP to zero, so that they do not  effect the simulation model.



  • 0
    •  Analog Employees 
    on Jan 19, 2016 10:11 PM

    Hello ,

    The CP gain bit is used in conjunction with the timeout value...for details explanation ...see page 13 of the datasheet , paragraph "Timer Counter Control",



  • Hello,

    I attached the open loop plot picture file of my DRO. (VCO.jpg)

    When I connect the loop filter which I designed using ADIsimPLL, the spectum of output seems sweeping as attached picture. (Closed Loop.jpg)

    I tried the other topology from ADIsimPLL, but it was the same result.

    I think the loop filter which I used is BPF, not LPF type. it doesn't pass the low frequency. So, it doesn't lock at all.

    Would you tell me your opinion?

    Please advice me how I can lock the signal. (Attached the circuit files)

    Thank you very much for your helping.