HMC699 Differential active loop filter help

Hi There,


I have inherited a design which uses a HMC699 Integer N PLL chip to lock an external VCO @ 4.6GHz using an external 10MHz reference clock.


http://www.synergymwave.com/products/vco/datasheet/DCYS250510-5.pdf


The Up/Down PFD outputs are connected to an differential active OP amp loop filter using the same circuit as found in the application circuit within the data sheet:-


http://www.analog.com/media/en/technical-documentation/data-sheets/hmc699.pdf


Does anyone have any literature regarding the proper design of the differential active loop filter to use with the two output digital PFD.


Are there any old Hittite application notes that have been removed that talk about the component selection for an optimum loop filter.


Unfortunately ADISimPLL (v4.00.04) only has a few Hittite pll chips to choose from but only single output charge pump types.


I can get the loop to lock – sort of, but with very high spurs and I am having to provide about +12dBm input power at the reference input which is outside the suggested operating limit maximum of +10dBm.


Can the the PLL really work with a 10MHz sine wave Refrence clock??


Any suggestions anyone

Cheers

 

Dan

  • 0
    •  Analog Employees 
    on Mar 2, 2016 3:45 AM

    Hi Dan,

    You can use the legacy Hittite PLL Design software and the attached tutorial that we’ve put together.  Ignore the website information in the attachment, and instead download the software from this link:  https://ez.analog.com/message/243415#243415

    Also, we are working to add the integer PFD parts into ADIsimPLL, so that we will have one common design tool for all PLL’s.


    With regard to the reference input signal, you will need a healthy amplitude level with a 10MHz sine wave.  The device is edge triggered and a fast rise time will provide best phase noise performance.  It is best to use a square wave if available.


    Best Regards,

    David

    UsingtheHMCPLLDesignToolforSynthesizerswithaPFDOutput.pdf
  • Hi David,

    Please can you qualify what you mean by "healthy". I can get the PLL to lock my 4.6GHz VCO if i put about +11dBm into the reference port at 10MHz but the data sheet says +5dBm max and +10dBm absolute maximum.

    I have also tried putting my 10MHz reference through a Texas Instruments SN74AHC1G04DBVR Inverter to square it up and to boost the signal level still further. The inclusion of the inverter gate actually degrades the phase noise somewhat despite the steeper edges and the TTL voltage levels.

    I have measured the input power @ 4.6GHz to the chip and this is about +4.7dBm which is on the high side of the spec but tshould be ok.

    In a previous project a HMC698 was used to lock the same VCO to 4.6GHz but with a sine wave 100MHz reference. In this set up the PLL happily locked the VCO with a reference input as low as -1dBm!!!.

    Can the HMC699 part really work with a 10MHz Reference or is there some other internal limiting factor within the chip?

    cheers

    Dan



  • 0
    •  Analog Employees 
    on Mar 11, 2016 4:10 AM

    Hi Dan,

    A healthy reference signal would be a square wave at +5dBm without any strange edge perturbations.

    The HMC699 will operate at 10MHz reference.  One thing to check is the series capacitor on the REF input.  At 10MHz input, you are going to want a large value, as to not degrade the amplitude that is presented to the device.

    Best Regards,

    David

  • Hi David,

    Thanks for the help on this.

    Ok so the HMC699PLL chip is only beginning to lock albeit with quite a poor phase noise performance with a 10MHz reference of around +12dBm which is really high. The 10MHz reference spurs are about -55dBc which is odd as the loop filter closed loop BW is set to about 100KHz.

    I have a 100nF series capacitor connected to the REF input ( Xc = 0.16 ohms @10MHz) and the same on the N_ref pin - As indicated on the application circuit in the datasheet. Both Ref & N ref have a DC voltage of about 3.1V on them which is the same for the HMC698 part.

    I have checked the signal level and quality on the the Ref pin and can see that it is a sensible level - with a 1M DC probe i am measuring about 0.4V.

    There is no 10MHz present on the n_ref pin as expected as this is coupled to ground via the 100nF capacitor.

    I have measure the RF power at the VCO input (by disconnecting the coupling capacitor and probing with a spectrum analyzer) and this is also around +5dBm.

    So im confident that there is at least +5dBm on both the Reference and RF inputs - which should allow sensible performance.

    I have used the the values taken straight off the design tool for the PFD active loop filter in the hope i could get it to lock with a sensible ref input power and then fine tune the loop filter to optimized the phase noise performance.

    I will attempt to make some pcb modifications to alter the divide ratio from 460 to 46 to allow me to use a 100MHz Ref CLK in an attempt to compare the performance to my other PCB which uses the HMC698.

    The chip does run very hot (+45 degree C) which might be expected for 1.75W power consumption.

    Any other suggestions?

  • 0
    •  Analog Employees 
    on Mar 15, 2016 2:22 AM

    Hi Dan,

    The +20C rise from ambient is normal for this particular device.  I would confirm the loop filter is as you intended for each reference frequency.

    Best Regards,

    David