I have inherited a design which uses a HMC699 Integer N PLL chip to lock an external VCO @ 4.6GHz using an external 10MHz reference clock.
The Up/Down PFD outputs are connected to an differential active OP amp loop filter using the same circuit as found in the application circuit within the data sheet:-
Does anyone have any literature regarding the proper design of the differential active loop filter to use with the two output digital PFD.
Are there any old Hittite application notes that have been removed that talk about the component selection for an optimum loop filter.
Unfortunately ADISimPLL (v4.00.04) only has a few Hittite pll chips to choose from but only single output charge pump types.
I can get the loop to lock – sort of, but with very high spurs and I am having to provide about +12dBm input power at the reference input which is outside the suggested operating limit maximum of +10dBm.
Can the the PLL really work with a 10MHz sine wave Refrence clock??
Any suggestions anyone