Post Go back to editing

Request a review about a circuit diagram with HMC721LP3E


My customer use HMC721LP3E for the purpose of clock doubling.

(Input datarate is 3Gbps and output datarate is 6Gbps)

And they have some problem about the device damage on their system.

So they are trying to find the reason why HMC721LP3E is damaged.

Q1) Would you confirm their circuit diagram and verify the reason why HMC721LP3E is damaged?

Please refer below circuit diagram and let me know your opinions.

And as below diagram, they are use 100ohm resistor at the output of HMC721 to adjust the Vref voltage of FPGA (DEVICE in diagram).

They guess that the reverse current from VTT source to HMC721 may cause this device damage problem.

Q2) Would you let them know the specification of absolute maximum current from VTT source to VEE pin or DP/DN pins?

      (It means how much current can be allowed in HMC721 if the reverse current is applied from the output pin (DP/DN) to internal VEE path in HMC722 or vice versa.)

Q3) Would you confirm the power ON/OFF sequence of their system in below diagram If HMC721 need any specific power sequence?

They are using below sequences.

  - Power ON sequence : Vee à GND à VR à VTT à memory device voltage

  - Power OFF sequence : memory device voltage à VTT à VR à GND à Vee


If you have any questions, please let me know.



Parents Reply Children
No Data