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running two PLL of HMC764

I have two evaluation boards of HMC764 that one is derived using its 50MHz internal clock and the other PLL is using this 50MHz clock as an external clock. When I set PLLs for the frequency around 7.5GHz  with 1MHz separation in frequency and just looking at one of the PLL's output using spectrum analyzer, I can see some spurious signals and its harmonics very close to fundamental frequency, 45KHz away from it and 35 dB below of it. Also, by changing the 1MHz separation between two PLLs  the  position of the spurious changes as well. it seems that some kind of modulation is happening between them.

What do you think is the reason of the phenomenon? are there any way to suppress it?

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  • Thanks for your complete answer and good suggested solutions.

    I just wondering what is the standard for reference clock signal of the HMC764? Is it LVDS ?

    In the evaluation board of the HMC764, the reference clock signal has been connected unbalanced (single ended), I'm wondering is it possible to connect a balanced crystal oscillator  to the PLL's chip (differential inputs) in order to cancel the common noise and improve the performance of the PLL? If we can use a differential signal as the clock to the PLL which matching circuit from crystal oscillator to the chip do you suggest?

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  • Thanks for your complete answer and good suggested solutions.

    I just wondering what is the standard for reference clock signal of the HMC764? Is it LVDS ?

    In the evaluation board of the HMC764, the reference clock signal has been connected unbalanced (single ended), I'm wondering is it possible to connect a balanced crystal oscillator  to the PLL's chip (differential inputs) in order to cancel the common noise and improve the performance of the PLL? If we can use a differential signal as the clock to the PLL which matching circuit from crystal oscillator to the chip do you suggest?

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