ADF4169 RSet

ADIsimPLL allows Rset to vary from 1.5K to 30K.  As Rset is changed, the loop bandwidth changes.  The ADF4169 datasheet specifies the Rset range as 4.59K to 5.61K.  In testing, varying Rset outside the specified range appears to vary the loop bandwidth.  What is the maximum usable range that Rset can be varied over? 

The datasheet also specifies the maximum Icp as 4.8 ma when RSet=5.1K.  By lowering Rset, how high can Icp be increased?

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  • Our technical support manager is Brett Gleadall.  I sent him an email earlier in the week regarding the digital lock detect signal.  Is there any chance you can help with this?

    We are using the ADF4169 with the HMC534.  In the attached pictures, I'm changing the frequency from 11.5 to 10.5 GHz.  The yellow is the digital lock detect, the green is V-tune and the purple is the detected RF.  Sometimes the lock detect is correct, other times it isn't.  If the frequency change is less than ~500 MHz (250 MHz at the ADF4169), then the lock detect is usually valid, but for larger frequency changes it is generally not valid.  The PLL is designed (ADIsimPLL) with a phase margin that varies between 51 and 61 degrees depending on the tuned frequency. LOL is enabled, LDP is set to 1 and the chip is configured for Integer mode (Register 4 set to 38000004) (The chip setup is attached).  What is the proper way to configure the ADF4169 to achieve a valid lock detect?

    Thanks

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  • Our technical support manager is Brett Gleadall.  I sent him an email earlier in the week regarding the digital lock detect signal.  Is there any chance you can help with this?

    We are using the ADF4169 with the HMC534.  In the attached pictures, I'm changing the frequency from 11.5 to 10.5 GHz.  The yellow is the digital lock detect, the green is V-tune and the purple is the detected RF.  Sometimes the lock detect is correct, other times it isn't.  If the frequency change is less than ~500 MHz (250 MHz at the ADF4169), then the lock detect is usually valid, but for larger frequency changes it is generally not valid.  The PLL is designed (ADIsimPLL) with a phase margin that varies between 51 and 61 degrees depending on the tuned frequency. LOL is enabled, LDP is set to 1 and the chip is configured for Integer mode (Register 4 set to 38000004) (The chip setup is attached).  What is the proper way to configure the ADF4169 to achieve a valid lock detect?

    Thanks

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