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ADF4169 RSet

ADIsimPLL allows Rset to vary from 1.5K to 30K.  As Rset is changed, the loop bandwidth changes.  The ADF4169 datasheet specifies the Rset range as 4.59K to 5.61K.  In testing, varying Rset outside the specified range appears to vary the loop bandwidth.  What is the maximum usable range that Rset can be varied over? 

The datasheet also specifies the maximum Icp as 4.8 ma when RSet=5.1K.  By lowering Rset, how high can Icp be increased?

  • The guaranteed RSET range is the range in the datasheet. It may be possible to use RSET outside this range but it is not characterized and not guaranteed to operate normally.

    The highest Icp = 24.48 ÷ 4.59 kΩ = 5.33 mA.

    Why do you need a higher charge pump current? If you use ADIsimPLL to select filter components for a wider loop bandwidth that will have the same effect as a higher charge pump current. I recommend designing your loop filter for the mid-point charge pump current so you have some flexibility to tweak the loop dynamic after building the filter components onto a board.

  • We are trying to design a PLL with selectable loop bandwidths.  RSet seemed like an easy place to switch in different resistors values.  Our plan was to change RSet between two values and also to change one of the loop capacitors that between V-Tune and ground between two values.

  • Can you use the programmable charge pump current (R2[27:24]) to get a similar effect?

  • We are using CSR for fast settling times.  Does it override the programmable charge pump current setting?  When using the ADF4169 Software, when CSR is enabled, changing the charge pump current doesn't appear to do anything.

  • I see. When using CSR, you need to program the minimum charge pump current. Then, when CSR is active, internally, it temporarily jumps to the maximum charge pump current.

    Maybe, instead of switching the RSET resistor, switch another one of the loop filter components.

  • Our technical support manager is Brett Gleadall.  I sent him an email earlier in the week regarding the digital lock detect signal.  Is there any chance you can help with this?

    We are using the ADF4169 with the HMC534.  In the attached pictures, I'm changing the frequency from 11.5 to 10.5 GHz.  The yellow is the digital lock detect, the green is V-tune and the purple is the detected RF.  Sometimes the lock detect is correct, other times it isn't.  If the frequency change is less than ~500 MHz (250 MHz at the ADF4169), then the lock detect is usually valid, but for larger frequency changes it is generally not valid.  The PLL is designed (ADIsimPLL) with a phase margin that varies between 51 and 61 degrees depending on the tuned frequency. LOL is enabled, LDP is set to 1 and the chip is configured for Integer mode (Register 4 set to 38000004) (The chip setup is attached).  What is the proper way to configure the ADF4169 to achieve a valid lock detect?


  • I just sent a reply back via Brett. This is the reply I sent:

    What does invalid mean? The ‘valid’ attachment was sent twice; I presume one was supposed to be ‘invalid’.

    Digital Lock Detect isn’t very robust on the ADDF4159/ADF4169. There may not be a way to improve on the current performance. One thing to try is to toggle the Lock Detect Precision bit in R3. This will tweak the lock detect timing window and may help.

    By the way, if you're using a 62.5 MHz PFD frequency and 5500 MHz RF frequency, you can use the ADF4159. The ADF4159 and ADF4169 are the same except the ADF4169 is guaranteed for higher frequencies (which you don't appear to be using).

  • Oops sorry about that, I attached the same picture twice.  Attached is the invalid lock ...

    So, do you toggle LDP before each tune?

  • Not toggle before each tune. Just experiment with LDP = 0. In the invalid image, it looks like lock detect is asserting too early. By setting LDP = 0, it will change the lock detect timing window. Hopefully, this window will be suited to your application and give a more reliable lock detect signal.

    If not, you may need to add a delay in your system after lock detect goes high to mitigate early assertion.

    Alternatively, you could somehow monitor the VTUNE signal and wait for a steady voltage level. Once the voltage level is steady, you know the loop is locked.

  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin