I want to multiply a 5MHz clock to 500MHz （or 10M to 1GHz ）, in this process, the phase noise that the frequency multiplier brings should be the least. And I find the integrated PLL chip HMC830 is a good choice.meanwhile the combination of these chips hmc984(the intergrated digital frequency and phase detector),hmc983(the integrated divider),hmc510(the integrated VCO) also can achieve the desired effect. so compare these two ways ,which one is the best?
Use the HMC830. This part has the integrated output divider to divide the internal 1500MHz to 3000MHz VCO down to 500MHz. The HMC510 VCO will not work down to 500MHz.
You can also use a discrete solution with the HMC704 PLL (this is the same PLL inside the HMC830). Select a low noise 500MHz VCO keeping in mind you have a minimum N=20 restriction in the PLL. With any reference below 25MHz this works fine since N>20. Now you don't need any output divider. The 5 or 10MHz reference would also be from a low phase noise source. Use the HMC1060 or HMC860 LDO's for power and select a low noise opamp for the loop filter.