ADF4355-2 close-in frequency independent spur problem

Hello,

We're having an issue with a design that implements an ADF4355-2. The problem? well, this is how the output looks like while set to an integer multiple of the reference frequency:

The reference frequency is 122,88 MHz, derived from a TI dual loop PLL (LMK04821) and the ADF was set to 1966,08 MHz (16*122,88) so we shouldn't have integer boundary problems. We basically use a very stable 24,576 MHz reference to stabilize a very low phase noise VCXO through a first PLL, and then that stable 122,88 MHz signal drives a secondary frequency synthesizer which then gets divided to get all the clock references, including ADF4355's. Due to a still unknown issue (this is a prototype  and we're starting to debug it) the first PLL of the LMK not always locks so it disables and the secondary PLL takes the reference directly from the VCXO which produces an extremely clean signal (no spurs there) but with some frequency error and slow drift, as can be seen in the capture (about 153 Hz error). When it does lock the frequency is spot-on but today I couldn't get it to lock, however the spur problem happens anyway.

These close-in spurs happen no matter what frequency we set the ADF to. They reduce their levels when output frequency is lower.

The ADF4355-2 is driven by the official  ADI Linux driver. Here's the loop filter:

The output you see in the captures was taken from RFOUTB-. RFOUTB- and RFOUTB+ are both terminated the same way with a 50 ohm load. RFOUTB+ goes straight to the load while RFOUTB- has a series Murata SWF connector (switch-disconnect) and we tap from there.

Here's the DTS instantiation:

adf4355-main@0 {

                    compatible = "adi,adf4355-2";

                    reg = <0>;

                    spi-max-frequency = <1000000>;

                    clocks = <0x8>;

                    clock-names = "clkin";

                    clock-output-names = "mainol";

                    adi,charge-pump-current = <900>;

                    adi,muxout-select = <6>;

                    adi,output-a-power = <3>;

                    adi,output-b-power = <3>;

                    adi,output-b-enable;

                    adi,output-a-enable;

                    adi,charge-pump-negative-bleed-enable;

                    adi,reference-differential-input-enable;

                    adi,power-up-frequency = /bits/ 64 <122880000>;

                };

clock 0x08 is set to 122,88 MHz. Clock reference is differential LVPECL.

Any clue about what might be happening?

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  • Yes there is a way, the clock distributor is outputting LVPECL 1600mV and it can be increased to LVPECL 2000mV. Will try it. That is for ADF4355 references, which are LVPECL differential AC-coupled.

    I have tried to sniff the PCB with a crude DIY E-field probe to see if there's any 83 kHz signal somewhere but found nothing at that frequency. I've also discarded a copule of charge-pump negative voltage generators that we use as these are switching at a higher and not harmonically related frequency.

    We've clocked ADF4351's:

    -Directly, from an E4438C agilent signal generator

    -From the Rakon VCXO included in the evaluation board

    -With a 10 MHz reference from an OCXO

    -With a 24.576 MHz reference derived from a 122.88 MHz crystal via a TI's CDCM6208v2 clock distributor

    -From a 24.576 MHz derived from 122.88 MHz VCXO and TCXO locked through an AD9511 in dual loop PLL mode

    All these times the reference signal is single-ended and AC-coupled, most times LVCMOS levels. We always have used ADI's linux drivers for controlling them.

    In this case the ADF4351 reference is single-ended LVCMOS at 122,88 MHz AC-coupled. We can't increase the power level in this reference. Apart from that nothing has changed too much, we've powered ADF4351's with ADP151's before, we always dedicate an SPI config bus to sensitive stuff which is quiet 99% of the time and the output topology (49.9 ohm to VCCRF) is something we've also used in other broadband designs. For ADF4355's we have pullup placeholders for inductors if neccesary but they are unpopulated, we use the internal 50 ohm resistors.

    I'll ask for permission to post the relevant parts of the schematic if you want to review them.

Reply
  • Yes there is a way, the clock distributor is outputting LVPECL 1600mV and it can be increased to LVPECL 2000mV. Will try it. That is for ADF4355 references, which are LVPECL differential AC-coupled.

    I have tried to sniff the PCB with a crude DIY E-field probe to see if there's any 83 kHz signal somewhere but found nothing at that frequency. I've also discarded a copule of charge-pump negative voltage generators that we use as these are switching at a higher and not harmonically related frequency.

    We've clocked ADF4351's:

    -Directly, from an E4438C agilent signal generator

    -From the Rakon VCXO included in the evaluation board

    -With a 10 MHz reference from an OCXO

    -With a 24.576 MHz reference derived from a 122.88 MHz crystal via a TI's CDCM6208v2 clock distributor

    -From a 24.576 MHz derived from 122.88 MHz VCXO and TCXO locked through an AD9511 in dual loop PLL mode

    All these times the reference signal is single-ended and AC-coupled, most times LVCMOS levels. We always have used ADI's linux drivers for controlling them.

    In this case the ADF4351 reference is single-ended LVCMOS at 122,88 MHz AC-coupled. We can't increase the power level in this reference. Apart from that nothing has changed too much, we've powered ADF4351's with ADP151's before, we always dedicate an SPI config bus to sensitive stuff which is quiet 99% of the time and the output topology (49.9 ohm to VCCRF) is something we've also used in other broadband designs. For ADF4355's we have pullup placeholders for inductors if neccesary but they are unpopulated, we use the internal 50 ohm resistors.

    I'll ask for permission to post the relevant parts of the schematic if you want to review them.

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