PHEMT bias sequencing circuit

Question

Hello. 
 I'm system engineer, so don't know well about PHEMT or HEMT chip. 
 I'd like to use HMC598 and HMC-ALH382, HMC-ALH476 like doubler or AMP. 
 These chips are required some bias sequence. 
 You can find PDF file about bias 
 //Design and Implementation of a Bias Sequencing Circuit for the HMC463LP5 Low Noise Amplifier// 
 that circuit is method how to make proper bais sequence. 
 They say VGG should be turned on than VDD. I understood it and It did good. 
 But, when VGG is turned off, is it okay? 
 I think VDD will be turnd off after VGG. It may be problems. 
 But that application note notice only tuned off speed by using VDD' capacitor. 
 Now, I want to know correct bias sequence. 
 Could I ignore bias when chips are turnd off?

dmailloux · Accepted Answer

Hi, 
 Generally, the biasing sequence for devices which have a gate voltage (amps, doublers) will be: 
 
 Apply gate voltage. 
 Apply drain voltage. 
 Apply RF. 
 
 The power down sequence should be those steps in reverse: 
 
 Remove RF. 
 Remove drain voltage. 
 Remove gate voltage. 
 
 Best Regards, 
 David)

ADIApproved · Answer

Hi Jeremy, 
 Yes datasheet min values are 3-4V for bias controllers. They can also work for lower Vdd values, depending on the DUT Idd requirement, the voltage drop may increase. On some applications people evaluate the bias controller and DUT configuration to see if they work with lower Vdd. I have seen some apps where 2.5Vdd is supplied thru HMC981. 
 Another way is using a series resistor at the Vdrain output of HMC980/1. This method is also used by some people at the expense of power consumption, see attached for an example apps circuit to bias HMC-ALH382 with HMC981. 
 Best, 
 Kagan

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PHEMT bias sequencing circuit